W167B
| Model | W167B |
| Description | 133-MHz Spread Spectrum FTG for Pentium II Platforms |
| PDF file | Total 18 pages (File size: 182K) |
| Chip Manufacturer | CYPRESS |
PRELIMINARY
Serial Data Interface
The W167B features a two-pin, serial data interface that can
be used to configure internal register settings that control par-
ticular device functions. Upon power-up, the W167B initializes
with default register settings, therefore the use of this serial
data interface is optional. The serial interface is write-only (to
the clock chip) and is the dedicated function of device pins
Table 2. Serial Data Interface Control Functions Summary
Control Function
Clock Output Disable
Description
Common Application
W167B
SDATA and SCLOCK. In motherboard applications, SDATA
and SCLOCK are typically driven by two logic outputs of the
chipset. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operation for power manage-
ment functions.
Table 2
summarizes the control functions of
the serial data interface.
Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI
abled outputs are actively held LOW.
and system power. Examples are clock out-
puts to unused SDRAM DIMM socket or PCI
slot.
Provides CPU/PCI frequency selections. Frequen-
cy is changed in a smooth and controlled fashion.
For alternate CPU devices, and power man-
agement options. Smooth frequency transi-
tion allows CPU frequency change under nor-
mal system operation.
Production PCB testing.
Production PCB testing.
CPU Clock Frequency
Selection
Output Three-state
Test Mode
(Reserved)
Operation
Puts all clock outputs into a high-impedance state.
All clock outputs toggle in relation with X1 input,
internal PLL is bypassed. Refer to
Table 4.
Reserved function for future device revision or pro- No user application. Register bit must be writ-
duction device testing.
ten as 0.
Data is written to the W167B in ten bytes of eight bits each. Bytes are written in the order shown in
Table 3.
Table 3. Byte Writing Sequence
Byte Sequence
1
Byte Name
Slave Address
Bit Sequence
11010010
Byte Description
Commands the W167B to accept the bits in Data Bytes 0–6 for internal
register configuration. Since other devices may exist on the same com-
mon serial data bus, it is necessary to have a specific slave address for
each potential receiver. The slave receiver address for the W167B is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
Unused by the W167B, therefore bit values are ignored (don’t care). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Command Code Byte is part of the standard serial com-
munication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
Unused by the W167B, therefore bit values are ignored (don’t care). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Byte Count Byte is part of the standard serial communi-
cation protocol and may be used when writing to another addressed
slave receiver on the serial data bus.
The data bits in these bytes set internal W167B registers that control
device operation. The data bits are only accepted when the Address
Byte bit sequence is 11010010, as noted above. For description of bit
control functions, refer to
Table 4,
Data Byte Serial Configuration Map.
2
Command
Code
Don’t Care
3
Byte Count
Don’t Care
4
5
6
7
8
9
10
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Refer to
Table 4
6
