W185-5
| Model | W185-5 |
| Description | Six Output Peak Reducing EMI Solution |
| PDF file | Total 8 pages (File size: 119K) |
| Chip Manufacturer | CYPRESS |
W185
Application Information
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in
Figure 4
should be used.
V
DD
decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the V
DD
pin as possible, otherwise the in-
R
Reference Output
Logic Input
XTAL Connection or Reference Input
XTAL Connection or NC
creased trace inductance will negate its decoupling capability.
The 10-µF decoupling capacitor shown should be a tantalum
type. For further EMI protection, the V
DD
connection can be
made via a ferrite bead, as shown.
Recommended Board Layout
Figure 5
shows a recommended 2-layer board layout.
1
2
3
4
5
6
7
8
9
10
11
12
W185
24
23
22
21
20
19
18
17
16
15
14
13
C2
0.1 µF
NC
Clock Output
Clock Output
R
Clock Output
R
C3
0.1 µF
R
Clock Output
Clock Output
Clock Output
R
R
R
C4
0.1 µF
C1
0.1 µF
3.3V or 5V System Supply
FB
C5
10 µF Tantalum
Figure 4. Recommended Circuit Configuration
C1....C4 =
High frequency supply decoupling
capacitor (0.1-µF recommended).
Xtal Connection or Reference Input
C2
G
C3
G
Xtal Connection or NC
C5 =
Common supply low frequency
decoupling capacitor (10-µF tantalum
recommended).
R =
Match value to line impedance
FB =
Ferrite Bead
G
G
R
G
Clock Output
R
=
Via To GND Plane
C4
G
R
C1
G
R
G
G
Power Supply Input
(3.3V or 5V)
FB
C5
Figure 5. Recommended Board Layout (2-Layer Board)
Ordering Information
Ordering Code
W185
W185-5
Document #: 38-00809-A
7
Package
Name
H
Package Type
24-Pin SSOP (209-mil)
