W19B160BBB7M
| Model | W19B160BBB7M |
| Description | Flash, 1MX16, 7ns, PBGA48, 6 X 8 MM, 0.80 MM PITCH, GREEN, TFBGA-48 |
| PDF file | Total 47 pages (File size: 628K) |
| Chip Manufacturer | WINBOND |
W19B160BT/B DATA SHEET
To access the auto select codes in-system, the host system can issue the auto select command
through the command register. This method does not require V
ID
. Also refer to the auto select
Command Sequence section for more information.
6.1.10 Sector Protection and Un-protection
The sector protection feature will disable both program and erase operations in any sectors. The
sector un-protection feature will re-enables both program and erase operations in previously protected
sectors. Sector protection / un-protection can be implemented through two methods.
The primary method requires V
ID
on the #RESET pin, and can be implemented either in-system or
through programming equipment. This method uses standard microprocessor bus cycle timing.
The alternate method intended only for programming equipment requires V
ID
on address pin A9 and
#OE It is possible to determine whether a sector is protected or unprotected. See the auto select
Mode section for details.
6.1.11 Temporary Sector Unprotect
This feature allows temporary un-protection of previously protected sectors to change data in-system.
When the #RESET pin is set to V
ID
, the Sector Unprotect mode is activated. During this mode,
formerly protected sectors can be programmed or erased by selecting the sector addresses. What if
V
ID
is removed from the #RESET pin, all the previously protected sectors are protected again.
6.1.12 Hardware Data Protection
The command sequence requirements of unlock cycles for programming or erasing provides data
protection against negligent writes. In addition, the following hardware data protection measures
prevent inadvertent erasure or programming, which might be caused by spurious system level signals
during V
DD
power-up and power-down transitions, or from system noise.
6.1.13 Write Pulse “Glitch” Protection
Noise pulses, which is less than 5nS (typical) on #OE, #CE or #WE, do not initiate a write cycle.
6.1.14 Logical Inhibit
Write cycles are inhibited by holding any one of #OE = V
IL
, #CE = V
IH
or #WE = V
IH
. #CE and #WE
must be a logical zero while #OE is a logical one to initiate a write cycle.
6.1.15 Power-Up Write Inhibit
During power up, if #WE = #CE = V
IL
and #OE = V
IH
, the device does not accept commands on the
rising edge of #WE. The internal state machine is automatically reset to the read mode on power-up.
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Publication Release Date Dec,30, 2008
Revision A8
