X1228V14-4.5A
| Model | X1228V14-4.5A |
| Description | Real Time Clock/Calendar/CPU Supervisor with EEPROM |
| PDF file | Total 31 pages (File size: 569K) |
| Chip Manufacturer | XICOR |
X1228
Figure 5. Set V
TRIP
Level Sequence (V
CC
= desired V
TRIP
value)
RESET
V
CC
0 1 2 3 4 5 6 7
SCL
V
P
= 15V
V
CC
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SDA
AEh
Note:
BP0, BP1, BP2 must be disabled.
00h
01h
00h
Resetting the V
TRIP
Voltage
This procedure is used to set the V
TRIP
to a “native”
voltage level. For example, if the current V
TRIP
is 4.4V
and the new V
TRIP
must be 4.0V, then the V
TRIP
must
be reset. When V
TRIP
is reset, the new V
TRIP
is some-
thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.
To reset the new V
TRIP
voltage, apply more than 5.5V
to the V
CC
pin and tie the RESET pin to the
programming voltage V
P
. Then write 00h to address
03h. The stop bit of a valid write operation initiates the
V
TRIP
programming sequence. Bring RESET to V
CC
to
complete the operation.
Note:
this operation takes up
Figure 6. Reset V
TRIP
Level Sequence
to 10 milliseconds to complete and also writes 00h to
address 03h of the EEPROM array.
For best accuracy in setting V
TRIP
, it is advised that the
following sequence be used.
1.Program V
TRIP
as above.
2.Measure resulting V
TRIP
by measuring the V
CC
value where a RESET occurs. Calculate Delta =
(Desired – Measured) V
TRIP
value.
3.Perform a V
TRIP
program using the following formula
to set the voltage of the RESET pin:
V
RESET
= (Desired Value – Delta) + 0.025V
RESET
V
CC
0 1 2 3 4 5 6 7
SCL
SDA
AEh
Note:
BP0, BP1, BP2 must be disabled.
V
P
= 15V
V
CC
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
00h
03h
00h
REV 1.3 3/24/04
www.xicor.com
Characteristics subject to change without notice.
17 of 31
Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 X1228V14-4.5A
|
Real Time Clock/Calendar/CPU Supervisor with EEPROM | INTERSIL | Preview |
