X1287S14I-4.5A
| Model | X1287S14I-4.5A |
| Description | Real Time Clock, Volatile, CMOS, PDSO14, PLASTIC, SOIC-14 |
| PDF file | Total 26 pages (File size: 304K) |
| Chip Manufacturer | RENESAS |
X1287
A write to a protected block of memory is ignored, but
will still receive an acknowledge. At the end of the
write command, the X1287 will not initiate an internal
write cycle, and will continue to ACK commands.
Page Write
The X1287 has a page write operation. It is initiated in
the same manner as the byte write operation; but
instead of terminating the write cycle after the first
data byte is transferred, the master can transmit up to
63 more bytes to the memory array and up to 7 more
bytes to the clock/control registers. (Note: Prior to writ-
ing to the CCR, the master must write a 02h, then 06h
to the status register in two preceding operations to
enable the write operation. See “Writing to the Clock/
Control Registers” on page 6.)
After the receipt of each byte, the X1287 responds
with an acknowledge, and the address is internally
incremented by one. When the counter reaches the
end of the page, it “rolls over” and goes back to the
first address on the same page. This means that the
master can write 64 bytes to a memory array page or 8
bytes to a CCR section starting at any location on that
page. If the master begins writing at location 40 of the
Figure 13. Page Write Sequence
Signals from
the Master
S
t
a
r
t
memory and loads 30 bytes, then the first 23 bytes are
written to addresses 40 through 63, and the last 7
bytes are written to columns 0 through 6. Afterwards,
the address counter would point to location 7 on the
page that was just written. If the master supplies more
than the maximum bytes in a page, then the previously
loaded data is over written by the new data, one byte
at a time.
The master terminates the Data Byte loading by issu-
ing a stop condition, which causes the X1287 to begin
the nonvolatile write cycle. As with the byte write oper-
ation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 13 for the address,
acknowledge, and data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the X1287 resets itself without per-
forming the write. The contents of the array are not
affected.
PR
EL
IM
IN
A
A
C
K
A
C
K
Data
R
Data
(1)
Y
S
t
o
p
(1
≤
n
≤64)
Word
Address 0
Data
(n)
Slave
Address
Word
Address 1
S
t
o
p
SDA Bus
1
1 1 10
0 0 0 0 0
Signals from
the Slave
A
C
K
A
C
K
A
C
K
Figure 14. Current Address Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
t
1
Slave
Address
1 1 11
Characteristics subject to change without notice.
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