X1287S14I-4.5A
| Model | X1287S14I-4.5A |
| Description | Real Time Clock, Volatile, CMOS, PDSO14, PLASTIC, SOIC-14 |
| PDF file | Total 26 pages (File size: 304K) |
| Chip Manufacturer | RENESAS |
X1287
Table 3. Block Protect Bits
BP2
BP1
BP0
Protected
Addresses
X1287
None
6000h - 7FFFh
4000h - 7FFFh
0000h - 7FFFh
0000h - 003Fh
0000h - 007Fh
0000h - 00FFh
0000h - 01FFh
None
Upper 1/4
Upper 1/2
Full Array
First Page
First 2 pgs
First 4 pgs
First 8 Pgs
Array Lock
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
frequency compensation. With the combination of
digital and analog trimming can give up to 90ppm
adjustment! The current design
ATR0
is a 0.5pf when
it equals to 1,
ATR1
is a 1pf when it equals to 1,
ATR2
is a 2pf when it equals to 1,
ATR3
is a 4pf when it
equals to 1,
ATR4
is a 7pf when it equals to 1 and
ATR5
is a 12.5pf when it equals to
0!
When all bits are
zero the loading capacitance is equal to 12.5pf that is
for “Seiko VT200” crystal as a default loading. There is
also a fixed 10pf capacitance for X1 and X2.
WRITING TO THE CLOCK/CONTROL REGISTERS
Table 4. Watchdog Timer Time Out Options
WD1 WD0
0
0
1
1
0
1
0
1
Watchdog Time-Out Period
1.75 Seconds
750 milliseconds
250 milliseconds
Disabled
PR
EL
IM
Digital Trimming Register (DTR)—DTR2, DFTR1
and DTR0-(Nonvolatile)
The digital trimming Bits
DTR2
,
DTR1
and
DTR0
adjust the number of count per second and average
the ppm error to achieve a better time over a long
period.
DTR2
is a sign when equal to 1 means positive
ppm and 0 means negative ppm compensation.
DTR1
will give 10 ppm adjustment and
DTR2
will give 20ppm
adjustment. A range from -30ppm to +30ppm can be
represented by using three bits above.
Analog Trimming Register (ATR)—ATR5, ATR4...
and ATR0-(Nonvolatile)
Six analog trimming Bits from
ATR5
to
DTR0
are pro-
vided to adjust the on-chip loading capacitance range
from 10pf to 39.5pf for X1 and X2. The effective load
capacitance range from 5pf to 19.75pf. Each bit has
different weight for capacitance adjustment. This will
allow 6pf or 12.5pf crystal being used and widen the
selection. Also it provides +60ppm to -40ppm a better
IN
The bits WD1 and WD0 control the period of the
Watchdog Timer. See Table 4 for options.
—Write a 06H to the Status Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
—Write one to 8 bytes to the Clock/Control Registers
with the desired clock, alarm, or control data. This
sequence starts with a start bit, requires a slave byte
of “11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
EEPROM values so these initiate a nonvolatile write
cycle and will take up to 10ms to complete. Writes to
undefined areas have no effect. The RWEL bit is
reset by the completion of a nonvolatile write write
cycle, so the sequence must be repeated to again
initiate another change to the CCR contents. If the
sequence is not completed for any reason (by send-
ing an incorrect number of bits or sending a start
instead of a stop, for example) the RWEL bit is not
reset and the device remains in an active mode.
—Writing all zeros to the status register resets both
the WEL and RWEL bits.
—A read operation occurring between any of the pre-
vious operations will not interrupt the register write
operation.
—The RWEL and WEL bits can be reset by writing a 0
to the Status Register.
A
Watchdog Timer Control Bits
—Write a 02H to the Status Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop).
R
Changing any of the nonvolatile bits of the clock/con-
trol register requires the following steps:
Y
Characteristics subject to change without notice.
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