M1040-11I155.5200
| Model | M1040-11I155.5200 |
| Description | VCSO BASED CLOCK PLL WITH AUTOSWITCH |
| PDF file | Total 12 pages (File size: 429K) |
| Chip Manufacturer | ICS |
M1040
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
Preliminary Information
D
ETAILED
B
LOCK
D
IAGRAM
M1040
NBW
MUX
nDIF_REF1
Auto
INIT
LOL
Ref Sel
0
1
LOL
Phase
Detector
FOUT0
nFOUT0
FOUT1
nFOUT1
P_SEL
Figure 3: Detailed Block Diagram
PLL D
IVIDER
S
ELECTION
T
ABLES
M and R Divider Look-Up Tables (LUT)
The
MR_SEL2:0
pins select the feedback and reference
divider values M and R to enable adjustment of loop
bandwidth and jitter tolerance. The look-up is defined in
Table 3.
M1040 M/R Divider LUT
Phase Det.
Total
Fin for
Freq. for
MR_SEL3:0
M Div R Div PLL
155.52MHz
155.52MHz
Ratio VCSO (MHz)
VCSO (MHz)
General Guidelines for M and R Divider Selection
General guidelines for M/R divider selection (see
following pages for more detail):
•
A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking,
especially during GR-253 jitter tolerance testing. The
recommended maximum phase detector frequency
for loop timing mode is
19.44MHz
. The
LOL
pin should
not be used during loop timing mode.
When
LOL
is to be used for system health monitoring,
the phase detector frequency should be
5MHz
or
greater. Low phase detector frequencies make
LOL
overly sensitive, and higher phase detector
frequencies make
LOL
less sensitive.
The preceding guideline also applies when using the
AutoSwitch Mode, since AutoSwitch uses the
LOL
output for clock fault detection.
•
000
001
010
011
100
101
110
111
8
64
2
16
1
8
2
1
8
1
8
1
8
8
8
8
2
2
1
1
N/A
0.25
19.44
19.44
77.76
77.76
155.52
155.52
N/A
622.08
19.44
2.43
77.76
9.72
155.52
19.44
N/A
77.76
•
Post-PLL Divider
The M1040 also features a post-PLL (P) divider for the
output clocks. It divides the VCSO frequency to produce
one of two selectable output frequencies (1/2 or 1/1 of
the VCSO frequency). That selected frequency appears
on both clock output pairs. The
P_SEL
pin selects the
value for the P divider.
P_SEL
Test Mode
1
Table 3: M1040 M/R Divider LUT
Note 1: Factory test mode; do not use.
Table 3
provides example Fin and phase detector
frequencies with
155.52MHz
VCSO devices
(e.g.,
M1040-11-155.5200).
See “Ordering Information”
on pg. 12.
P Value
2
1
1
0
Output Frequency
(MHz)
77.76
155.52
M1040-11-155.52
Table 4: P Divider Selector Values and Frequencies
M1040 Datasheet Rev 0.1
●
3 of 12
●
Revised 11Nov2003
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tel (508) 852-5400
