M1040-11I155.5200
| Model | M1040-11I155.5200 |
| Description | VCSO BASED CLOCK PLL WITH AUTOSWITCH |
| PDF file | Total 12 pages (File size: 429K) |
| Chip Manufacturer | ICS |
PLL Operation
The M1040 is a complete clock PLL. It uses a phase
detector and configurable dividers to synchronize the
output of the VCSO with the selected reference clock.
The “M” divider divides the VCSO output frequency,
feeding the result into the plus input of the phase
detector. The output of the “R” divider is fed into the
minus input of the phase detector. The phase detector
compares its two inputs. The phase detector output,
filtered externally, causes the VCSO to increase or
decrease in speed as needed to phase- and
frequency-lock the VCSO to the reference input.
The value of the M divider directly affects closed loop
bandwidth.
M1040
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
Preliminary Information
Loss of Lock Indicator Output Pin
Under normal device operation, when the PLL is locked,
the LOL Phase Detector drives
LOL
to logic
0
. Under
circumstances when the VCSO cannot lock to the input
(as measured by a greater than 4 ns discrepancy
between the feedback and reference clock rising edges
at the LOL Phase Detector) the
LOL
output goes to logic
1. The
LOL
pin will return back to logic
0
when the phase
detector error is less than 2 ns. The loss of lock
indicator is a low current LVCMOS output.
Guidelines Using LOL
As described, the
LOL
pin indicates when the PLL is
The relationship between the nominal VCSO center
frequency (Fvcso), the M divider, the R divider, and the
input reference frequency (Fin) is:
M
-
Fvcso
=
Fin
×
---
R
For the available M divider and R divider look-up table
combinations,
Tables 3 and 4 on pg. 3
list the Total PLL
Ratio as well as Fin when using the
M1040-11-155.5200
.
(See “Ordering Information”, pg. 12.)
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
Post-PLL Divider
The M1040 features a post-PLL (P) divider. By using
the P Divider, the device’s output frequency (Fout) can
be the VCSO center frequency (Fvcso) or 1/2 Fvcso.
The
P_SEL
pin selects the value for the P divider: logic
1
sets P to
2,
logic
0
sets P to
1
. (See Table 5 on pg. 6.)
When the P divider is included, the complete relation-
ship for the output frequency (Fout) is defined as:
M
Fvcso
-
Fout
=
-------------------
=
Fin
×
-----------------
P
R
×
P
out-of-lock with the input reference.
The LOL condition
is also used by the AutoSwitch circuit to detect a lost
reference, as described in following sections. LOL is
also used by the Hitless Switching and Phase Build-out
functions (optional device features). To ensure reliable
operation of LOL and guard against false out-of-lock
indications, the following conditions should be met:
•
The phase detector frequency should be no less than
Phase detector frequency is defined by
Fin / R.
A higher phase detector frequency will result in lower
phase error and less chance of false triggering the
LOL phase detector. Refer to Tables 3 and 4 on pg. 3
for phase detector frequency when using the
M1040-11-155.5200
.
The input reference should have an intrinsic jitter of
less than 1 ns pk-pk. If reference jitter is greater than
1 ns pk-pk, the LOL circuit might falsely trigger. Due
to this limitation, the LOL circuit should not be used in
loop timing mode, nor should it be used with a noisy
reference clock. Likewise, the AutoSwitch, Hitless
Switching, or Phase Build-out features should not be
used in loop timing mode or with a noisy reference
clock, since these features depend on LOL.
5MHz
, and preferably it should be
10MHz
or greater.
•
Reference Acknowledgement (REF_ACK) Output
The
REF_ACK
(reference acknowledgement) pin outputs
the value of the reference clock input that is routed to
the phase detector. Logic
1
indicates input pair
1
(
nDIF_REF1, DIF_REF1
);
l
ogic
0
indicates input pair
0
(
nDIF_REF0, DIF_REF0
)
.
The
REF_ACK
indicator is an
LVCMOS output.
M1040 Datasheet Rev 0.1
●
5 of 12
●
Revised 11Nov2003
●
tel (508) 852-5400
