M11B1644SA-60T
| Model | M11B1644SA-60T |
| Description | EDO DRAM, 4MX4, 60ns, CMOS, PDSO24, TSOP2-26/24 |
| PDF file | Total 16 pages (File size: 200K) |
| Chip Manufacturer | ESMT |
$ %
DRAM
FEATURES
y
y
y
M11B1644A / M11B1644SA
M11L1644A / M11L1644SA
4M x 4 DRAM
EDO PAGE MODE
ORDERING INFORMATION - PACKAGE
24 / 26-pin 300mil SOJ
24 / 26-pin 300mil TSOP (TypeII)
PRODUCT NO.
M11B1644A-45J/50J/60J
M11B1644SA-45J/50J/60J
M11L1644A-45J/50J/60J
M11L1644SA-45J/50J/60J
M11B1644A-45T/50T/60T
M11B1644SA-45T/50T/60T
M11L1644A-45T/50T/60T
M11L1644SA-45T/50T/60T
* Ordered by special request
Refresh Vcc
Normal
*Self-
Refresh
Normal
Self-
Refresh
Normal
*Self-
Refresh
Normal
Self-
Refresh
3.3V
5V
TSOPII
3.3V
5V
SOJ
PACKING
TYPE
y
y
y
y
y
y
X4 organization
EDO (Extended Data-Out) access mode
Single power supply :
5V
±
10% Vcc for 5V product
3.3V
±
10% Vcc for 3.3V product
Interface for inputs and outputs
TTL-compatible for 5V products
LVTTL-compatible for 3.3V products
2048-cycle refresh in 32ms
Refresh modes :
RAS
only,
CAS
BEFORE
RAS
(CBR)
and HIDDEN capabilities,
Optional self-Refresh capabilities(S-ver. Only)
JEDEC standard pinout
Key AC Parameter
-45
-50
-60
t
RAC
45
50
60
t
CAC
11
13
15
t
RC
77
84
104
t
PC
16
20
25
GENERAL DESCRIPTION
The M11B1644/M11L1644 series is a randomly accessed solid state memory, organized as 4,194,304 x 4 bits device. It
offers Extended Data-Output access mode. Single power supply (5V
±
10%, 3.3V
±
10%), access time (-45,-50,-60), self-
refresh function and package type (SOJ, TSOP II) are optional features of this family. All these family have
CAS
- before -
RAS
,
RAS
-only refresh and Hidden refresh.
The primary advantage of EDO is the availability of data-out even after
CAS
returns high. EDO allows
CAS
precharge
time (t
PC
) to occur without the output data going invalid. This elimination of
CAS
output control allows pipeline Read.
PIN ASSIGNMENT
SOJ Top View
V
CC
I/ O0
I/ O1
WE
R AS
NC
A10
A0
A1
A2
A3
V
CC
TSOP (TypeII) Top View
V
S S
I /O 3
I /O 2
C AS
OE
A9
A8
A7
A6
A5
A4
V
S S
V
CC
I/O 0
I/O 1
WE
RA S
NC
A10
A0
A1
A2
A3
V
C C
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
SS
I/ O3
I/ O2
CA S
OE
A9
A8
A7
A6
A5
A4
V
SS
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2001
Revision
:
1.1
1/16
