M11L16161SA-50T
| Model | M11L16161SA-50T |
| Description | EDO DRAM, 1MX16, 50ns, CMOS, PDSO44, TSOP2-50/44 |
| PDF file | Total 16 pages (File size: 203K) |
| Chip Manufacturer | ESMT |
$ %
FUNCTIONAL BLOCK DIAGRAM
WE
RAS
CASL
CASH
CONTROL
LOGIC
M11B16161A / M11B16161SA
M11L16161A / M11L16161SA
DATA-IN BUFFER
16
IO0
:
IO15
CLOCK
GENERATOR
DATA-OUT
BUFFER
COLUMN
10
DECODER
1024
16
OE
16
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
10
COLUMN
ADDRESS
BUFFER
REFRESH
CONTROLER
SENSE AMPLIFIERS
I/O GATING
8
1024 x 16
REFRESH
COUNTER
10
ROW.
ADDRESS
BUFFERS(10)
10
ROW
DECODER
1024
1024 x 1024 x 16
MEMORY
ARRAY
V
CC
V
BB
GENERATOR
V
SS
PIN DESCRIPTIONS
PIN NO.
(SOJ Package)
17~20, 23~28
14
30
31
13
29
2~5,7~10,33~36,38~41
1,6,21
22,37,42
11,12,15,16,32
PIN NAME
TYPE
DESCRIPTION
Address Input
Row Address : A0~A9
Column Address : A0~A9
Row Address Strobe
Column Address Strobe / Upper Byte Control
Column Address Strobe / Lower Byte Control
Write Enable
Output Enable
Data Input / Output
Power, (5V or 3.3V)
Ground
No Connect
A0~A9
RAS
CASH
CASL
WE
OE
Input
Input
Input
Input
Input
Input
Input / Output
Supply
Ground
-
I/O0 ~ I/O15
V
CC
V
SS
NC
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2001
Revision
:
1.3
2/16
