N04L163WC1C
| Model | N04L163WC1C |
| Description | 4Mb Ultra-Low Power Asynchronous CMOS SRAM |
| PDF file | Total 10 pages (File size: 263K) |
| Chip Manufacturer | ETC |
N04L163WC1C
NanoAmp Solutions, Inc.
Functional Block Diagram
Advance Information
Address
Inputs
A0 - A3
Word
Address
Decode
Logic
Address
Inputs
A4 - A17
Page
Address
Decode
Logic
16K Page
x 16 word
x 16 bit
RAM Array
Input/
Output
Mux
and
Buffers
Word Mux
I/O0 - I/O7
I/O8 - I/O15
CE
WE
OE
UB
LB
Control
Logic
Functional Description
CE
H
X
L
L
L
WE
X
X
L
H
H
OE
X
X
X
3
L
H
UB
X
H
L
L
L
LB
X
H
L
L
L
I/O
0
- I/O
151
High Z
High Z
Data In
Data Out
High Z
MODE
Standby
2
Standby
Write
Read
Active
POWER
Standby
Standby
Active
Active
Active
1. When UB and LB are in select mode (low), I/O
0
- I/O
15
are affected as shown. When LB only is in the select mode only I/O
0
- I/O
7
are affected as shown. When UB is in the select mode only I/O
8
- I/O
15
are affected as shown.
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
Capacitance
1
Item
Input Capacitance
I/O Capacitance
Symbol
C
IN
C
I/O
Test Condition
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
Min
Max
10
10
Unit
pF
pF
1. These parameters are verified in device characterization and are not 100% tested
Stock No. 23373-C 1/05
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
2
