W144
| Model | W144 |
| Description | 440BX AGPset Spread Spectrum Frequency Synthesizer |
| PDF file | Total 14 pages (File size: 158K) |
| Chip Manufacturer | CYPRESS |
PRELIMINARY
DC Electrical Characteristics:
(continued)
T
A
= 0°C to +70°C; V
DDQ3
= 3.3V±5%; V
DDQ2
= 2.5V±5%
Parameter
Crystal Oscillator
V
TH
C
LOAD
C
IN,X1
C
IN
C
OUT
L
IN
X1 Input threshold Voltage
[5]
Load Capacitance, Imposed on
External Crystal
[6]
X1 Input Capacitance
[7]
Input Pin Capacitance
Output Pin Capacitance
Input Pin Inductance
Pin X2 unconnected
Except X1 and X2
V
DDQ3
= 3.3V
1.65
14
28
5
6
7
Description
Test Condition
Min.
Typ.
Max.
W144
Unit
V
pF
pF
pF
pF
nH
Pin Capacitance/Inductance
Notes:
3. All clock outputs loaded with 6" 60Ω traces with 22-pF capacitors.
4. W144 logic inputs (except FS3) have internal pull-up devices (pull-ups not full CMOS level). Logic input FS3 has an internal pull-down device.
5. X1 input threshold voltage (typical) is V
DDQ3
/2.
6. The W144 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is
14 pF; this includes typical stray capacitance of short PCB traces to crystal.
7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
AC Electrical Characteristics
T
A
= 0°C to +70°C; V
DDQ3
= 3.3V±5%; V
DDQ2
= 2.5V±5%; f
XTL
= 14.31818 MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum clocking is disabled.
CPU Clock Outputs, CPU_F, CPU1 (Lump Capacitance Test Load = 20 pF)
CPU = 66.6 MHz
Parameter
t
P
t
H
t
L
t
R
t
F
t
D
t
JC
Description
Period
High Time
Low Time
Output Fall Edge Rate
Duty Cycle
Jitter, Cycle-to-Cycle
Test Condition/Comments
Measured on rising edge at 1.25
Duration of clock cycle above 2.0V
Duration of clock cycle below 0.4V
Measured from 2.0V to 0.4V
Measured on rising and falling edge at
1.25V
Measured on rising edge at 1.25V. Max-
imum difference of cycle time between
two adjacent cycles.
Measured on rising edge at 1.25V
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
Average value during switching transi-
tion. Used for determining series termi-
nation value.
20
15
5.6
5.3
1.5
1.5
45
4
4
55
200
15.5
CPU = 100 MHz
10
3.3
3.1
1.5
1.5
45
4
4
55
200
10.5
ns
ns
ns
V/ns
V/ns
%
ps
Min. Typ. Max. Min. Typ. Max. Unit
Output Rise Edge Rate Measured from 0.4V to 2.0V
t
SK
f
ST
Output Skew
Frequency Stabiliza-
tion from Power-up
(cold start)
AC Output Impedance
250
3
250
3
ps
ms
Z
o
20
Ω
10
