W144
| Model | W144 |
| Description | 440BX AGPset Spread Spectrum Frequency Synthesizer |
| PDF file | Total 14 pages (File size: 158K) |
| Chip Manufacturer | CYPRESS |
PRELIMINARY
Writing Data Bytes
Each bit in Data Bytes 0–7 controls a particular device function
except for the “reserved” bits, which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit 7.
Table 5
gives the bit formats for registers located in Data Bytes
0–7.
Table 5. Data Bytes 0-7 Serial Configuration Map
Affected Pin
Bit(s)
7
6
5
4
3
2
1–0
Pin No.
--
--
--
--
--
--
--
Pin Name
--
--
--
--
--
--
--
(Reserved)
SEL_2
SEL_1
SEL_0
Hardware/Software Frequency Select
SEL_3
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Control Function
0
--
See
Table 6
See
Table 6
See
Table 6
Hardware
Software
See
Table 6
Function (See
Table 7
for function details)
Normal Operation
(Reserved)
Spread Spectrum On
All Outputs Three-stated
--
--
--
--
Low
--
Low
Low
--
Low
--
Low
Low
Low
Low
Low
--
--
Low
Low
--
Low
--
--
--
--
Active
--
Active
Active
--
Active
--
Active
Active
Active
Active
Active
--
--
Active
Active
--
Active
Data Byte 0
--
Bit Control
1
W144
Table 6
details additional frequency selections that are avail-
able through the serial data interface.
Table 7
details the select functions for Byte 0, bits 1 and 0.
Default
0
0
0
0
0
0
00
Data Byte 1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Data Byte 3
7
6
5
4
3
2
--
--
26
25
--
21, 20,
18, 17
--
--
48MHz
24MHz
--
SDRAM8:11
(Reserved)
(Reserved)
Clock Output Disable
Clock Output Disable
(Reserved)
Clock Output Disable
0
0
1
1
0
1
--
--
--
--
40
--
43
44
--
7
--
13
12
11
10
8
--
--
--
--
SDRAM_F
--
CPU1
CPU_F
--
PCI_F
--
PCI5
PCI4
PCI3
PCI2
PCI1
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Clock Output Disable
(Reserved)
Clock Output Disable
Clock Output Disable
(Reserved)
Clock Output Disable
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
1
Data Byte 2
6
