W161H
| Model | W161H |
| Description | Processor Specific Clock Generator, 133MHz, CMOS, PDSO48, 0.300 INCH, MO-118AA, SSOP-48 |
| PDF file | Total 10 pages (File size: 115K) |
| Chip Manufacturer | CYPRESS |
PRELIMINARY
W161
133-MHz Spread Spectrum FTG for Pentium® II Platforms
Features
• Maximized EMI Suppression using Cypress’s Spread
Spectrum Technology
• Three copies of CPU outputs at 100 or 133 MHz
• Three copies of 66-MHz output at 3.3V
• Ten copies of PCI clocks at 33 MHz, 3.3V
• Two copies of 14.318-MHz reference output at 3.3V
• One copy of 48-MHz USB clock
• One copy of CPU-divide-by-2 output as reference input
to Direct Rambus™ Clock Generator (Cypress W134)
• Available in 48-pin SSOP (300 mils)
Spread Spectrum Modulation:..................................... –0.5%
CPU to 3V66 Output Offset: ............. 0.0–1.5 ns (CPU leads)
3V66 to PCI Output Offset:.............. 1.5–3.0 ns (3V66 leads)
CPU to IOAPIC Output Offset: ......... 1.5–4.0 ns (CPU leads)
Table 1. Pin Selectable Frequency
SEL133/100# SEL1 SEL0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Function
All outputs Three-State
(Reserved)
Active 100-MHz, 48-MHz
PLL inactive
Active 100-MHz, 48-MHz
PLL active
Test Mode
(Reserved)
Active 133-MHz, 48-MHz
PLL inactive
Active 133-MHz, 48-MHz
PLL active
Key Specifications
Supply Voltages: ...................................... V
DDQ2
= 2.5V±5%
V
DDQ3
= 3.3V±5%
CPU, CPUdiv2 Output Jitter:....................................... 250 ps
CPU, CPUdiv2 Output Skew:...................................... 175 ps
IOAPIC, 3V66 Output Skew:....................................... 250 ps
PCI0:9 Output Skew: .................................................. 500 ps
Duty Cycle: ................................................................... 45/55
Block Diagram
X1
X2
Pin Configuration
[1]
XTAL
OSC
2
REF_[0:1]
3
CPU_[0:2]
SPREAD#
SEL0
SEL1
SEL133/100#
÷2
CPUdiv2
PLL 1
3
÷2/÷1.5
3V66_[0:2]
9
PWRDWN#
÷2
PCI_[0:9]
Power
Down
Logic
÷2
IOAPIC
REF0
REF1
VDDQ3
X1
X2
GND
PCI0
PCI1
VDDQ3
PCI2
PCI3
PCI4
PCI5
GND
PCI6
PCI7
VDDQ3
PCI8
PCI9
GND
3V66_0
3V66_1
3V66_2
VDDQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
VDDQ2
IOAPIC
GND
VDDQ2
CPUdiv2
GND
VDDQ2
CPU2
GND
VDDQ2
CPU1
CPU0
GND
VDDQ3
GND
PWRDWN#*
SPREAD#*
SEL1*
SEL0*
VDDQ3
48MHz
GND
SEL133/100#
Note:
1. Internal 250-k
Ω
pull-up resistors present on inputs marked with *.
Design should not rely solely on internal pull-up resistor to set I/O
pins HIGH.
W161
Three-state
Logic
PLL2
48MHz
Pentium is a registered trademark of Intel Corporation. Direct Rambus is a trademark of Rambus, Inc.
Cypress Semiconductor Corporation
Document #: 38-07162 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 25, 2001
