W167B
| Model | W167B |
| Description | 133-MHz Spread Spectrum FTG for Pentium II Platforms |
| PDF file | Total 18 pages (File size: 182K) |
| Chip Manufacturer | CYPRESS |
PRELIMINARY
W167B
133-MHz Spread Spectrum FTG for Pentium® II Platforms
Features
• Maximized EMI Suppression using Cypress’s Spread
Spectrum technology
• Three copies of CPU outputs selectable frequency
• Three copies of 3V66 selectable frequency output at
3.3V
• Ten copies of PCI clocks (selectable frequency), 3.3V
• One double strength 14.318-MHz reference output at
3.3V
• One copy of 48-MHz USB clock
• One copy of selectable 24-/48-MHz for SIO
• One copy of CPU-divide-by-2 output as reference input
to Direct Rambus™ Clock Generator (Cypress W134)
• Three copies of IOAPIC
• Available in 48-pin SSOP (300 mils)
Duty Cycle: ................................................................ 45/55%
Spread Spectrum Modulation:................................... ±0.25%
CPU to 3V66 Output Offset: ............. 0.0–1.5 ns (CPU leads)
3V66 to PCI Output Offset:.............. 1.5–4.0 ns (3V66 leads)
CPU to IOAPIC Output Offset: ......... 1.5–4.0 ns (CPU leads)
Table 1. Pin Selectable Frequency
SEL133/
CPU
100# SEL2 SEL1 SEL0 MHz
1
1
1
1
133.3
1
1
1
0
138
1
1
0
1
143
1
1
0
0
148
1
0
1
1
150
1
0
1
0
152.5
1
0
0
1
155
1
0
0
0
160
0
1
1
1
100.2
0
1
1
0
105
0
1
0
1
114
0
1
0
0
120
0
0
1
1
66.8
0
0
1
0
124
0
0
0
1
128.5
0
0
0
0
133.9
3V66
MHz
66.7
69
71.5
74
75
76.3
77.5
80
66.8
70
76
80
66.8
82.7
64.3
67
PCI IOAPIC
MHz MHz
33.3 16.7
34.5 17.3
35.8 17.9
37
18.5
37.5 18.8
38.1 19.1
38.8 19.4
40
20
33.4 16.7
35
17.5
38
19
40
20
33.4 16.7
41.3 20.7
32.1 16.1
33.5 16.7
Key Specifications
Supply Voltages: ...................................... V
DDQ2
= 2.5V±5%
V
DDQ3
= 3.3V±5%
CPU, CPUdiv2 Output Jitter:....................................... 250 ps
CPU, CPUdiv2 Output Skew: ...................................... 175 ps
IOAPIC, 3V66 Output Skew: ....................................... 250 ps
PCI0:8 Pin to Pin Skew: .............................................. 500 ps
Block Diagram
VDDQ3
X1
X2
Pin Configuration
REF2X
[1]
XTAL
OSC
VDDQ2
CPU_[0:2]
3
÷2
SEL133/100#
CPUdiv2
VDDQ3
PLL 1
÷2/÷1.5
3V66_[0:2]
3
PCI0/SEL2*
PCI1/SEL1*
÷2
8
PCI_[2:9]
PWRDWN#
Power
Down
Logic
VDDQ2
÷2
3
IOAPIC[0:2]
IOAPIC2
REF2X
VDDQ3
X1
X2
GND
SEL2*/PCI0
SEL1*/PCI1
VDDQ3
PCI2
PCI3
PCI4
PCI5
GND
PCI6
PCI7
VDDQ3
PCI8
PCI9
GND
3V66_0
3V66_1
3V66_2
VDDQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
VDDQ2
IOAPIC0
IOAPIC1
GND
VDDQ2
CPUdiv2
GND
VDDQ2
CPU2
GND
VDDQ2
CPU1
CPU0
SDATA
VDDQ3
GND
PWRDN#*
SCLK
VDDQ3
Q#
VDDQ3
PLL2
48MHz/SEL0*
Note:
1. Internal 250-kΩ pull-up resistors present on inputs marked with *.
Design should not rely solely on internal pull-up resistor to set I/O
pins HIGH.
W167B
SIO/24_48#MHz
*
48MHz/SEL0*
GND
SEL133/100#
SDATA
SCLK
÷2
Serial
Logic
SIO/24_48#MHz
Direct Rambus is a trademark of Rambus, Inc. Pentium is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
November 2, 1999
