W19B320ATB7L
| Model | W19B320ATB7L |
| Description | Flash, 2MX16, 70ns, PBGA48, 6 X 8 MM, 0.80 MM PITCH, TFBGA-48 |
| PDF file | Total 53 pages (File size: 479K) |
| Chip Manufacturer | WINBOND |
W19B320AT/B
8.3 DC Characteristics
8.3.1
CMOS Compatible
PARAMETER
Input Load Current
A9 Input Load Current
Output Leakage Current
V
DD
Active Read Current
(Note 1, 2)
SYM.
I
LI
I
LIT
I
LO
TEST CONDITIONS
MIN.
V
IN
=V
SS
to V
DD
, V
DD
= V
DD
(Max.)
V
DD
= V
DD
(Max.), A9 = 12.5V
V
OUT
=V
SS
to V
DD
, V
DD
=V
DD
(Max.)
-
-
-
-
LIMITS
TYP.
-
-
-
10
2
10
2
15
0.2
0.2
0.2
21
21
21
21
17
5
15
-
-
-
UNIT
MAX.
±1.0
35
±1.0
16
4
16
4
30
5
5
5
45
45
45
45
35
10
30
0.8
V
DD
+0.3
9.5
μA
μA
μA
mA
mA
mA
mA
mA
μA
μA
μA
mA
mA
mA
mA
mA
V
V
V
#CE
= V
IL,
#OE
= V
IH
I
CC1
Byte Mode
#CE
= V
IL
,
#OE
= V
IH
Word Mode
5 MHz
1 MHz
5 MHz
1 MHz
V
DD
Active Write Current
(Note 2, 3)
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
CC7
I
CC8
I
Acc
V
IL
V
IH
V
HH
#CE
= V
IL,
#OE
= V
IH,
#WE
= V
IL
#CE
= V
DD
±0.3V,
#RESET
= V
DD
±0.3V
-
-
-
-
-
-
-
-
-
V
DD
Standby Current
(Note2)
V
DD
Reset Current
(Note2)
#RESET
= V
SS
±0.3V
V
IH
= V
DD
±0.3V,
V
IL
= V
SS
±0.3V
Automatic Sleep Mode
Current
(note 2, 4)
V
DD
Active Read-While-
Program
Current
(note 1, 2)
V
DD
Active Read-While-
Erase
Current (note 1, 2)
V
DD
Active Program-While-
Erase-Suspended
Current
(note 2, 5)
#CE
= V
IL,
#OE
= V
IH
#CE
= V
IL,
#OE
= V
IH
#CE
= V
IL,
#OE
= V
IH
#CE =
V
IL,
#OE =
V
IH
-
-
V
DD
=3.0V
±10%
Byte
Word
Byte
Word
ACC Accelerated Program
Current, Word or Byte
Input Low Voltage
Input High Voltage
Voltage for #WP/ACC Sector
Protect/ Unprotect and
Program Acceleration
Voltage for AUTOSELECT
and Temporary Sector
Unprotected
Output Low Voltage
Output High Voltage
Low V
DD
Lock-Out Voltage
Notes:
1.
2.
3.
4.
ACC Pin
V
DD
Pin
-0.5
0.7x V
DD
8.5
V
ID
V
OL
V
OH1
V
OH2
V
LKO
V
DD
=3.0V
±10%
I
OL
= 4.0 mA, V
DD
= V
DD
(Min.)
I
OH
= -2.0 mA, V
DD
= V
DD
(Min.)
I
OH
= -100
μA,
V
DD
= V
DD
(Min.)
8.5
-
0.85 V
DD
V
DD -
0.4
2.3
-
-
-
-
-
12.5
0.45
-
-
2.5
V
V
V
V
The I
CC
current listed is typically less than 2 mA/ MHz, with #OE at V
IH
.
Maximum I
CC
specifications are tested with V
DD
= V
DD
max.
I
CC
active while Embedded Erase or Embedded Program is in progress.
Automatic sleep mode enables the low power mode when addresses remain stable for t
ACC
+ 30 ns. Typical sleep mode
current is200 nA.
- 37 -
Publication Release Date: December 27, 2005
Revision A4
