W19B320ATB7L
| Model | W19B320ATB7L |
| Description | Flash, 2MX16, 70ns, PBGA48, 6 X 8 MM, 0.80 MM PITCH, TFBGA-48 |
| PDF file | Total 53 pages (File size: 479K) |
| Chip Manufacturer | WINBOND |
W19B320AT/B
8.10 Alternate #CE Controlled Erase and Program Operations
70 NS
PARAMETER
SYM.
MIN.
TYPICAL
(NOTE3)
MAX.
(NOTE4)
UNIT
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Read Recover Time Before Write (#OE High
to #WE Low)
#WE Setup Time
#WE Hold Time
#CE Pulse Width
#CE Pulse Width High
Programming Time (Note 6)
Accelerated Programming
Time (Note 6)
Sector Erase Time (Note 2)
Chip Erase Time (Note 2)
Chip Program Time (Note 5)
Notes:
1. Not 100 % tested.
TWC
TAS
TAH
TDS
TDH
TGHEL
TWS
TWH
TCP
TCPH
Byte
Word
Byte
Word
TPB
TPW
TACCP
TSE
TCE
Byte
Word
70
0
45
35
0
0
0
0
30
30
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
7
4
0.4
49
21
14
-
-
-
-
-
-
-
-
-
-
150
210
120
15
-
63
42
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
μ
s
sec
sec
sec
TCPB
T
CPW
2. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
3. Typical program and erase time assume the following conditions :25℃,3.0 V V
DD
, 100,000 cycles .Additionally,
programming typicals assume checkerboard pattern.
4. Under worst case conditions of 90℃, V
DD
=2.7V, 100,000 cycles.
5. The typical chip programming time is considerably less than the maximun chip programming time listed,since most
bytes program faster than maximun program times listed.
6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.
7. The device has a minimum erase and program cycle endurance of 100,000 cycles.
- 41 -
Publication Release Date: December 27, 2005
Revision A4
