X1286V14I
| Model | X1286V14I |
| Description | Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM X1286 |
| PDF file | Total 25 pages (File size: 362K) |
| Chip Manufacturer | INTERSIL |
X1286
Table 1. Clock/Control Memory Map
(Continued)
Reg
Name
Y2K0
DWA0
YRA0
MOA0
DTA0
HRA0
MNA0
SCA0
EMO0
EDT0
EHR0
EMN0
ESC0
EDW0
0
0
0
0
A0M22
A0S22
0
0
A0D21
A0H21
A0M21
A0S21
0
7
6
5
4
0
A0G20
A0D20
A0H20
A0M20
A0S20
3
0
A0G13
A0D13
A0H13
A0M13
A0S13
2
DY2
A0G12
A0D12
A0H12
A0M12
A0S12
1
DY1
A0G11
A0D11
A0H11
A0M11
A0S11
(optional)
Addr.
0007
0006
0005
0004
0003
0002
0001
0000
Type
Alarm0
(EEPROM)
Range
20
0-6
1-12
1-31
0-23
0-59
0-59
Read-only - Default = 20h
DY0
A0G10
A0D10
A0H10
A0M10
A0S10
Unused - Default = RTC Year value (No EEPROM) – Future expansion
20h
00h
00h
00h
00h
00h
00h
When there is a match, an alarm flag is set. The occur-
rence of an alarm can be determined by polling the
AL0 and AL1 bits or by enabling the IRQ output, using
it as hardware flag.
The alarm enable bits are located in the MSB of the
particular register. When all enable bits are set to ‘0’,
there are no alarms.
– The user can set the X1286 to alarm every Wednes-
day at 8:00 AM by setting the EDWn*, the EHRn*
and EMNn* enable bits to ‘1’ and setting the DWAn*,
HRAn* and MNAn* Alarm registers to 8:00 AM
Wednesday.
– A daily alarm for 9:30PM results when the EHRn*
and EMNn* enable bits are set to ‘1’ and the HRAn*
and MNAn* registers are set to 9:30 PM.
*n = 0 for Alarm 0: N = 1 for Alarm 1
REAL TIME CLOCK REGISTERS
Clock/Calendar Registers (SSEC, SC, MN, HR, DT,
MO, YR)
These registers depict BCD representations of the
time. As such, SSEC (1/100 Second) range from 00 to
99, SC (Seconds) and MN (Minutes) range from 00 to
59, HR (Hour) is 1 to 12 with an AM or PM indicator
(H21 bit) or 0 to 23 (with MIL=1), DT (Date) is 1 to 31,
MO (Month) is 1 to 12, YR (Year) is 0 to 99. The SSEC
register is read-only.
Date of the Week Register (DW)
This register provides a Day of the Week status and
uses three bits DY2 to DY0 to represent the seven
days of the week. The counter advances in the cycle
0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical
value to a specific day of the week is arbitrary and may
be decided by the system software designer. The
default value is defined as ‘0’.
24 Hour Time
If the MIL bit of the HR register is 1, the RTC uses a
24-hour format. If the MIL bit is 0, the RTC uses a 12-
hour format and H21 bit functions as an AM/PM indi-
cator with a ‘1’ representing PM. The clock defaults to
standard time with H21=0.
Leap Years
Leap years add the day February 29 and are defined
as those years that are divisible by 4. Years divisible
by 100 are not leap years, unless they are also divisi-
ble by 400. This means that the year 2000 is a leap
year, the year 2100 is not. The X1286 does not correct
for the leap year in the year 2100.
STATUS REGISTER (SR)
The Status Register is located in the CCR memory
map at address 003Fh. This is a volatile register only
and is used to control the WEL and RWEL write
enable latches, read two power status and two alarm
bits. This register is separate from both the array and
the Clock/Control Registers (CCR).
Table 2. Status Register (SR)
Addr
003Fh
Default
7
BAT
0
6
AL1
0
5
AL0
0
4
0
0
3
0
0
2
RWEL
0
1
WEL
0
0
RTCF
1
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating
from V
BACK
, not V
CC
. It is a read-only bit and is set/reset
by hardware (X1286 interally). Once the device begins
operating from V
CC
, the device sets this bit to “0”.
11
FN8101.0
March 29, 2005
Default
Bit
Related PDFs
| Model | Description | Manufacturer | Operation |
|---|---|---|---|
 X1286V14I-T1
|
1 TIMER(S), REAL TIME CLOCK, PDSO14, 4.40 MM, PLASTIC, TSSOP-14 | RENESAS | Preview |
