X1286V14I
Model | X1286V14I |
Description | Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM X1286 |
PDF file | Total 25 pages (File size: 362K) |
Chip Manufacturer | INTERSIL |
X1286
AC Specifications
(T
A
= -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.)
Symbol
f
SCL
t
IN
t
AA
t
BUF
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
DH
t
R
t
F
Cb
SCL Clock Frequency
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus must be free before a new transmission can start
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive load for each bus line
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
20 +.1Cb
(1)(2)
20 +.1Cb
(1)(2)
300
300
400
50
(1)
0.9
Parameter
Min.
Max.
400
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
pF
Notes: (1) This parameter is not 100% tested.
(2) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
t
F
SCL
t
SU:STA
SDA IN
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
HIGH
t
LOW
t
R
t
AA
SDA OUT
t
DH
t
BUF
6
FN8101.0
March 29, 2005