Z0538001PSC
| Model | Z0538001PSC |
| Description | SMALL COMPUTER SYSTEM INTERFACE (SCSI) |
| PDF file | Total 37 pages (File size: 242K) |
| Chip Manufacturer | ZILOG |
Z
ILOG
The proposed SCSI specification also requires that no
more than two device ID’s be active during the selection
process. To ensure this, the Current SCSI Data Register is
read.
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register are displayed in Figures
14 and 15, respectively.
D7
0
0
0
1
X
0
X
D0
0
Z5380 SCSI
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register for this interrupt are
shown in Figures 16 and 17.
D7
1
0
0
1
0
0
0
D0
X
/ACK
/ATN
Busy Error
Phase Match
/ACK
Interrupt Request Active
/ATN
Parity Error
Busy Error
DMA Request
Phase Match
End of DMA
Interrupt Request Active
Parity Error
DMA Request
End of DMA
Figure 16. Bus and Status Register
Figure 14. Bus and Status Register
D7
0
1
1
X
X
X
0
D0
X
D7
0
0
0
X
X
X
0
D0
X
/DBP
/SEL
I//O
/DBP
/SEL
I//O
C//D
/MSG
/REQ
/BSY
/RST
C//D
/MSG
/REQ
/BSY
/RST
Figure 17. Current SCSI Bus Status Register
Figure 15. Current SCSI Bus Status Register
End Of Process (EOP) Interrupt
An End Of Process signal (EOP) which occurs during a
DMA transfer (DMA Mode True) will set the End of DMA
Status bit (bit 7) and will optionally generate an interrupt if
Enable EOP Interrupt bit (Mode Register, bit 3) is True. The
/EOP pulse will not be recognized (End of DMA bit set)
unless /EOP, /DACK, and either /IOR or /IOW are concur-
rently active for at least 100 ns. DMA transfers can still
occur if /EOP was not asserted at the correct time. This
interrupt is disabled by resetting the Enable EOP Interrupt
bit.
The End of DMA bit is used to determine when a block
transfer is complete. Receive operations are complete
when there is no data left in the chip and no additional
handshakes occurring. The only exception to this is receiv-
ing data as an Initiator and the Target opts to send
additional data for the same phase. In this /REQ goes
active and the new data is present in the Input Data
Register. Since a phase-mismatch interrupt will not occur,
/REQ and /ACK need to be sampled to determine that the
Target is attempting to send more data.
PS97SCC0100
PS009101-0201
11
