Z0538001PSC
| Model | Z0538001PSC |
| Description | SMALL COMPUTER SYSTEM INTERFACE (SCSI) |
| PDF file | Total 37 pages (File size: 242K) |
| Chip Manufacturer | ZILOG |
Z
ILOG
Z5380 SCSI
FUNCTIONAL DESCRIPTION
(Continued)
D7
0
0
0
1
X
1
0
D0
0
reading the Current SCSI Bus Status Register; however,
this signal is not latched and may not be present when this
port is read).
/ACK
/ATN
Busy Error
Phase Match
Interrupt Request Active
Parity Error
DMA Request
End of DMA
SCSI Bus Reset (/RST) Issued
If the CPU sets the Assert /RST bit (bit 7) in the Initiator
Command Register, the /RST signal goes active on the
SCSI Bus and an internal reset is performed. Again, all
internal logic and registers are cleared except for the IRQ
interrupt latch and the Assert /RST bit (bit 7) in the Initiator
Command Register. The /RST signal will continue to be
active until the Assert /RST bit is reset or until a hardware
reset occurs.
Data Transfers
Data is transferred between SCSI Bus devices in one of
four modes (Reference Figures 26-41):
1.
2.
3.
4.
Programmed I/O
Normal DMA
Block Mode DMA
Pseudo DMA
Figure 24. Bus and Status Register
D7
0
0
0
X
X
X
0
D0
0
/DBP
/SEL
I//O
C//D
/MSG
/REQ
/BSY
/RST
The following sections describe these modes in detail
(Note: For all data transfer operations, /DACK and /CS
should never be active simultaneously).
Programmed I/O Transfers
Programmed I/O is the most primitive form of data transfer.
The /REQ and /ACK handshake signals are individually
monitored and asserted by reading and writing the appro-
priate register bits. This type of transfer is normally used
when transferring small blocks of data such as command
blocks or message and status bytes. An Initiator send
operation would begin by setting the C//D, I//O, and /MSG
bits in the Target Command Register to the correct state so
that a phase match exists. In addition to the phase match
condition, it is necessary for the Assert Data Bus bit
(Initiator Command Register, bit 0) to be True and the
received I/O signal to be False for the Z5380 to send data.
For each transfer, the data is loaded into the Output Data
Register. The CPU then waits for the /REQ bit (Current SCSI
Bus Status Register, bit 5) to become active. Once /REQ
goes active, the Phase Match bit (Bus and Status Register,
bit 3) is checked and the Assert /ACK bit (Initiator Com-
mand Register, bit 4) is set. The /REQ bit is sampled until
it becomes False and the CPU resets the Assert /ACK bit
to complete the transfer.
Normal DMA Mode
DMA transfers are normally used for large block transfers.
The SCSI chip outputs a DMA request (DRQ) whenever it
is ready for a byte transfer. External DMA logic uses this
Figure 25. Current SCSI Bus Status Register
Reset Conditions
Three possible reset situations exist with the Z5380, as
follows:
Hardware Chip Reset
When the signal /RST is active for at least 200 ns, the Z5380
device is re-initialized and all internal logic and control
registers are cleared. This is a chip reset only and does not
create a SCSI Bus-Reset condition.
SCSI Bus Reset (/RST) Received
When a SCSI /RST signal is received, an IRQ interrupt is
generated and a chip reset is performed. All internal logic
and registers are cleared, except for the IRQ interrupt latch
and the Assert /RST bit (bit 7) in the Initiator Command
Register. (Note: The /RST signal may be sampled by
14
PS009101-0201
PS97SCC0100
