I1K-L67132L-45
| Model | I1K-L67132L-45 |
| Description | Dual-Port SRAM, 2KX8, 45ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48 |
| PDF file | Total 14 pages (File size: 178K) |
| Chip Manufacturer | TEMIC |
L67132/L67142
Timing Waveform of Contention Cycle n
o
2, Address Valid Abritration
(For L 67132 only)
(53)
Left Address Valid First :
Right Address Valid First :
Note :
53. CS
L
= CS
R
= V
IL
16 Bit Master/Slave Dual-port Memory Systems
Note :
54. No arbitration in L 67142 (SLAVE). BUSY-IN inhibits write in L 67142 (SLAVE).
MATRA MHS
Rev. D (19 Fev. 97)
13
