I1K-L67132L-45
| Model | I1K-L67132L-45 |
| Description | Dual-Port SRAM, 2KX8, 45ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48 |
| PDF file | Total 14 pages (File size: 178K) |
| Chip Manufacturer | TEMIC |
L67132/L67142
AC Parameters
WRITE CYCLE
PARAMETER
SYMBOL
(30)
TAVAVW
TELWH
TAVWH
TAVWL
TWLWH
TWHAX
TDVWH
TGHQZ
TWHDX
TWLQZ
TWHQX
Notes :
SYMBOL
(31)
t
WC
t
SW
t
AW
t
AS
t
WP
t
WR
t
DW
t
HZ
t
DH
t
WZ
t
OW
Write cycle time
Chip select to end of write (28)
Address valid to end of write
Address Set–up Time
Write Pulse Width
Write Recovery Time
Data Valid to end of write
Output high Z time (26, 27)
Data hold time (29)
Write enable to output in high Z (26, 27)
Output active from end of write (26, 27, 29)
L67132–45
L67142–45
MIN.
MAX.
L67132–55
L67142–55
MIN.
MAX.
L67132–70
L67142–70
MIN.
MAX.
UNIT
PRELIMINARY
45
35
35
0
35
0
25
–
0
–
0
–
–
–
–
–
–
–
20
–
20
–
55
40
40
0
40
0
25
–
0
–
0
–
–
–
–
–
–
–
30
–
30
–
70
45
45
0
45
0
30
–
0
–
0
–
–
–
–
–
–
–
40
–
40
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
26. Transition is measured
±
500 mV from low or high impedance voltage with load (figures 1 and 2).
27. This parameter is guaranteed but not tested.
28. To access RAM CS = VIL.
This condition must be valid for entire t
SW
time.
29. The specification for t
DH
must be met by the device supplying write data to the RAM under all operating conditions.
Although t
DH
and t
OW
values vary over voltage and temperature, the actual t
DH
will always be smaller than the actual t
OW
.
30. STD symbol.
31. ALT symbol.
8
MATRA MHS
Rev. D (19 Fev. 97)
