I1K-L67132L-45
| Model | I1K-L67132L-45 |
| Description | Dual-Port SRAM, 2KX8, 45ns, CMOS, CDIP48, 0.600 INCH, CERAMIC, DIP-48 |
| PDF file | Total 14 pages (File size: 178K) |
| Chip Manufacturer | TEMIC |
L67132/L67142
Truth Table
Table 1 : Non Contention Read/Write Control
(4)
LEFT OR RIGHT PORT
(1)
FUNCTION
R/W
X
L
H
H
Notes :
CS
H
L
L
L
OE
X
X
L
H
D0–7
Z
DATA
IN
DATA
OUT
Z
Port Disabled and in Power Down Mode. ICCSB or ICCSB1
Data on Port Written into memory
(2)
Data in Memory Output on Port
(3)
High Impedance Outputs
1. A
OL
– A
10L
≠
A
0R
– A
10R
.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see t
WDD
and t
DDD
timing.
4. H = HIGH, L = LOW, X = DON’T CARE, Z = HIGH IMPEDANCE.
Table 2 : Arbitration
(5)
LEFT PORT
CS
L
H
L
H
L
RIGHT PORT
CS
R
H
H
L
L
FLAGS
FUNCTION
BUSY
L
H
H
H
H
A
0L
– A
10L
X
Any
X
≠
A
0R
– A
10R
A
0L
– A
10R
X
X
Any
≠
A
0L
– A
10L
BUSY
R
H
H
H
H
No Contention
No Contention
No Contention
No Contention
ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH
L
L
L
L
LV5R
RV5L
Same
Same
L
L
L
L
LV5R
RV5L
Same
Same
H
L
H
L
L
H
L
H
L–Port Wins
R–Port Wins
Arbitration Resolved
Arbitration Resolved
CS ARBITRATION WITH ADDRESS MATCH BEFORE CS
LL5R
RL5L
LW5R
LW5R
Notes :
= A
0R
– A
10R
= A
0R
– A
10R
= A
0R –
A
10R
= A
0R
– A
10R
LL5R
RL5L
LW5R
LW5R
= A
0L
– A
10L
= A
0L –
A
10L
= A
0L
– A
10L
= A
0L
– A
10L
H
L
H
L
L
H
L
H
L–Port Wins
R–Port Wins
Arbitration Resolved
Arbitration Resolved
5. X = DON’T CARE, L = LOW, H = HIGH.
LV5R = Left Address Valid
≥
5 ns before right address.
RV5L = Right address Valid
≥
5 ns before left address.
Same = Left and Right Addresses match within 5 ns of each other.
LL5R = Left CS = LOW
≥
5 ns before Right CS.
RL5L = Right CS = LOW
≥
5 ns before left CS.
LW5R = Left and Right CS = LOW within 5 ns of each other.
4
MATRA MHS
Rev. D (19 Fev. 97)
