K1S3216B5C-FI700
| Model | K1S3216B5C-FI700 |
| Description | Pseudo Static RAM, 2MX16, 70ns, CMOS, PBGA48, 8 X 6 MM, 0.75 MM PITCH, FBGA-48 |
| PDF file | Total 10 pages (File size: 166K) |
| Chip Manufacturer | SAMSUNG |
K1S3216B5C
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, ZZ=WE=V
IH
, UB or LB=V
IL
)
t
RC
Address
t
OH
Data Out
Previous Data Valid
t
AA
Data Valid
Advanced
UtRAM
TIMING WAVEFORM OF READ CYCLE(2)
(ZZ=WE=V
IH
)
t
RC
Address
t
AA
CS
t
CO
t
HZ
t
BA
UB, LB
t
BHZ
t
OE
OE
t
LZ
t
OLZ
t
BLZ
Data Valid
t
OHZ
t
OH
Data out
(READ CYCLE)
High-Z
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
3. t
OE
(max) is met only when
OE
becomes enabled after t
AA
(max).
4. If invalid address signals shorter than min. t
RC
are continuously repeated for over 4us, the device needs a normal read timing(t
RC
) or
needs to sustain standby state for min. t
RC
at least once in every 4us.
-7-
Revision 0.1
May 2003
