K1S3216B5C-FI700
| Model | K1S3216B5C-FI700 |
| Description | Pseudo Static RAM, 2MX16, 70ns, CMOS, PBGA48, 8 X 6 MM, 0.75 MM PITCH, FBGA-48 |
| PDF file | Total 10 pages (File size: 166K) |
| Chip Manufacturer | SAMSUNG |
K1S3216B5C
TIMING WAVEFORM OF WRITE CYCLE(3)
(UB, LB Controlled
,
ZZ=V
IH
)
t
WC
Address
t
CW(2)
CS
t
AW
t
BW
UB, LB
t
AS(3)
t
WP(1)
WE
t
DW
Data in
Data Valid
t
DH
t
WR(4)
Advanced
UtRAM
Data out
(WRITE CYCLE)
High-Z
High-Z
1. A wri
t
e occurs during the overlap(t
WP
) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition
when CS goes high and WE goes high. The t
WP
is measured from the beginning of write to the end of write.
2. t
CW
is measured from the CS going low to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR
is applied in case a write ends with CS or WE going high.
TIMING WAVEFORM OF DEEP POWER DOWN MODE ENTRY AND EXIT
200µs
≈
ZZ
Normal Operation
MODE
0.5µs
Suspend
Wake up
Normal Operation
Deep Power Down Mode
≈
CS
(DEEP POWER DOWN MODE)
1. When you toggle ZZ pin low, the device gets into the Deep Power Down mode after 0.5µs suspend period.
2. To return to normal operation, the device needs Wake Up period.
3. Wake Up sequence is just the same as Power Up sequence.
-9-
Revision 0.1
May 2003
