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Home > Data Sheet > M11L416256SA-28T
M11L416256SA-28T

M11L416256SA-28T

Model M11L416256SA-28T
Description EDO DRAM, 256KX16, 28ns, CMOS, PDSO40, TSOP2-44/40
PDF file Total 16 pages (File size: 231K)
Chip Manufacturer ESMT
(OLWH07
FUNCTIONAL BLOCK DIAGRAM
WE
RAS
CASL
CASH
CONTROL
LOGIC
M11L416256A/M11L416256SA
DATA-IN BUFFER
16
IO0
:
IO15
CLOCK
GENERATOR
DATA-OUT
BUFFER
9
COLUMN
DECODER
512
16
OE
16
9
A0
A1
A2
A3
COLUMN
ADDRESS
BUFFER
REFRESH
CONTROLER
SENSE AMPLIFIERS
I/O GATING
8
512 x 16
A4
A5
A6
A7
A8
9
99
ROW.
ADDRESS
BUFFERS(9)
9
ROW
DECODER
512 x 512 x 16
MEMORY
ARRAY
REFRESH
COUNTER
512
V
CC
V
BB
GENERATOR
V
SS
PIN DESCRIPTIONS
PIN NO.
16~19,22~26
14
28
29
13
27
2~5,7~10,31~34,36~39
1,6,20
21,35,40
11,12,15,30
PIN NAME
A0~A8
RAS
CASH
CASL
WE
OE
TYPE
Input
Input
Input
Input
Input
Input
Input / Output
Supply
Ground
-
DESCRIPTION
Address Input
Row Address : A0~A8
Column Address : A0~A8
Row Address Strobe
Column Address Strobe / Upper Byte Control
Column Address Strobe / Lower Byte Control
Write Enable
Output Enable
Data Input / Output
Power, 3.3V
Ground
No Connect
I/O0 ~ I/O15
V
CC
V
SS
NC
Elite Memory Technology Inc
Publication Date: Agu. 2001
Revision
:
1.3
2/16
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