I3K-L67130V-45
| Model | I3K-L67130V-45 |
| Description | Dual-Port SRAM, 1KX8, 45ns, CMOS, PDIP48, 0.600 INCH, PLASTIC, DIP-48 |
| PDF file | Total 16 pages (File size: 196K) |
| Chip Manufacturer | TEMIC |
L67130/L67140
Timing Waveform of Write Cycle n
o
1, R/W Controlled Timing
(36, 37, 38, 42)
Timing Waveform of Write Cycle n
o
2, CS Controlled Timing
(36, 37, 38, 40)
Notes :
R/W must be high during all address transitions.
A write occurs during the overlap (t
SW
or t
WP
) of a low CS and a low R/W.
t
WR
is measured from the earlier of CS or R/W going high to the end of write cycle.
During this period, the I/O pins are in the output state, and input signals must not be applied.
If the CS low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high
impedance state.
41. Transition is measured
±
500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled
and not 100 % tested.
42. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
)
to allow the I/O drivers to turn off and data to be placed on the bus for the required t
DW
. If OE is high during an R/W
controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
WP
.
43. To access RAM, CS = VIL.
36.
37.
38.
39.
40.
10
MATRA MHS
Rev. D (19 Fev. 97)
