I3K-L67130V-45
| Model | I3K-L67130V-45 |
| Description | Dual-Port SRAM, 1KX8, 45ns, CMOS, PDIP48, 0.600 INCH, PLASTIC, DIP-48 |
| PDF file | Total 16 pages (File size: 196K) |
| Chip Manufacturer | TEMIC |
L67130/L67140
AC Parameters
SYMBOL
PARAMETER
L67130–45
L67140–45
MIN.
BUSY TIMING (For L 67130 only)
t
BAA
t
BDA
t
BAC
t
BDC
t
WDD
t
DDD
t
APS
t
BDD
BUSY Access time to address
BUSY Disable time to address
BUSY Access time to Chip Select
BUSY Disable time to Chip Select
Write Pulse to data delay (44)
Write data valid to read data delay (44)
Arbitration priority set–up time (45)
BUSY disable to valid data
–
–
–
–
–
–
5
–
35
35
30
25
70
45
–
Note 46
–
–
–
–
–
–
5
–
45
40
35
30
80
55
–
Note 46
–
–
–
–
–
–
5
–
50
40
50
40
90
70
–
Note 46
ns
ns
ns
ns
ns
ns
ns
ns
MAX.
L67130–55
L67140–55
MIN.
MAX.
L67130–70
L67140–70
MIN.
MAX.
UNIT
BUSY TIMING (For L 67140 only)
t
WB
t
WH
t
WDD
t
DDD
Notes :
Write to BUSY input (47)
Write hold after BUSY (48)
Write pulse to data delay (49)
Write data valid to read data delay (49)
0
30
–
–
–
–
70
45
0
30
–
–
–
–
80
55
0
30
–
–
–
–
90
70
ns
ns
ns
ns
44. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Read with
BUSY (For L67130 only)”.
45. To ensure that the earlier of the two ports wins.
46. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
– t
WP
(actual) or t
DDD
– t
DW
(actual).
47. To ensure that the write cycle is inhibited during contention.
48. To ensure that a write cycle is completed after contention.
49. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveforms of Read
with Port to port delay (For L67140 only)”.
MATRA MHS
Rev. D (19 Fev. 97)
11
