I3K-L67130V-45
| Model | I3K-L67130V-45 |
| Description | Dual-Port SRAM, 1KX8, 45ns, CMOS, PDIP48, 0.600 INCH, PLASTIC, DIP-48 |
| PDF file | Total 16 pages (File size: 196K) |
| Chip Manufacturer | TEMIC |
L67130/L67140
AC Parameters
READ CYCLE
PARAMETER
SYMBOL
(23)
TAVAVR
TAVQV
TELQV
TGLQV
TAVQX
TELQZ
TEHQZ
TPU
TPD
Notes :
20.
21.
22.
23.
24.
SYMBOL
(24)
t
RC
t
AA
t
ACS
t
AOE
t
OH
t
LZ
t
HZ
t
PU
t
PD
Read cycle time
Address access time
Chip Select access time (22)
Output enable access time
Output hold from address change
Output low Z time (20, 21)
Output high Z time (20, 21)
Chip Select to power up time (21)
Chip disable to power down time (21)
L67130–45
L67140–45
MIN.
MAX.
L67130–55
L67140–55
MIN.
MAX.
L67130–70
L67140–70
MIN.
MAX.
UNIT
PRELIMINARY
45
–
–
–
0
5
–
0
–
–
45
45
30
–
–
20
–
50
55
–
–
–
0
5
–
0
–
–
55
55
35
–
–
30
–
50
70
–
–
–
0
5
–
0
–
–
70
70
40
–
–
35
–
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
Transition is measured
±
500 mV from low or high impedance voltage with load (figures 1 and 2).
This parameter is guaranteed but not tested.
To access RAM CS = VIL.
STD symbol.
ALT symbol.
Timing Waveform of Read Cycle n
o
1, Either Side
(25, 26, 28)
Timing Waveform of Read Cycle n
o
2, Either Side
(25, 27, 29)
Notes :
25.
26.
27.
28.
29.
R/W is high for read cycles.
Device is continuously enabled, CS = VIL.
Addresses valid prior to or coincident with CS transition low.
OE = VIL.
To access RAM, CS = VIL.
8
MATRA MHS
Rev. D (19 Fev. 97)
