I3K-L67130V-45
| Model | I3K-L67130V-45 |
| Description | Dual-Port SRAM, 1KX8, 45ns, CMOS, PDIP48, 0.600 INCH, PLASTIC, DIP-48 |
| PDF file | Total 16 pages (File size: 196K) |
| Chip Manufacturer | TEMIC |
L67130/L67140
Waveform of Interrupt Timing
(59)
Notes :
59.
60.
61.
52.
All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
See interrupt truth table.
Timing depends on which enable signal is asserted last.
Timing depends on which enable signal is de-asserted first.
AC Electrical Characteristics over the Full
Operating Temperature and Supply Voltage Range
INTERRUPT
TIMING
SYMBOL
t
AS
t
WR
t
INS
t
INR
Address set–up time
Write recovery time
Interrupt set time
Interrupt reset time
L 67130/140–45
PARAMETER
MIN.
0
0
—
—
L 6 7130/140–55
MIN.
0
0
—
—
L 6 7130/140–70
UNIT
MIN.
0
0
—
—
MAX.
—
—
40
40
MAX.
—
—
45
45
MAX.
—
—
60
60
ns
ns
ns
ns
MATRA MHS
Rev. D (19 Fev. 97)
15
