I3K-L67130V-45
| Model | I3K-L67130V-45 |
| Description | Dual-Port SRAM, 1KX8, 45ns, CMOS, PDIP48, 0.600 INCH, PLASTIC, DIP-48 |
| PDF file | Total 16 pages (File size: 196K) |
| Chip Manufacturer | TEMIC |
L67130/L67140
Data-Retention Mode
MHS CMOS RAMs are designed with battery backup in
mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules insure
data retention :
1 – Chip select (CS) must be held high during data
retention ; within Vcc to VCC
DR
.
2 – CS must be kept between V
CC
– 0.2 V and 70 % of Vcc
during the power up and power down transitions.
3 – The RAM can begin operation > tRC after Vcc
reaches the minimum operating voltage (3 volts).
Timing
MAX
PARAMETER
TEST CONDITIONS (18)
COM
ICC
DR1
@ VCC
DR
= 2 V
10
MIL
IND
AUTO
20
UNIT
µA
Notes :
18. CS = Vcc, Vin = Gnd to Vcc.
19. t
RC
= Read cycle time.
AC Test Conditions
Input Pulse Levels : GND to 3.0 V
Input Rise/Fall Times : 5 ns
Input Timing Reference Levels : 1.5 V
Figure 1. Output Load.
Output Reference Levels : 1.5 V
Output Load : see figures 1, 2
Figure 2. Output load.
(For t
HZ
, t
LZ
, t
WZ
, and t
OW
)
MATRA MHS
Rev. D (19 Fev. 97)
7
