K1S1616B5M-EE70T
| Model | K1S1616B5M-EE70T |
| Description | DRAM |
| PDF file | Total 12 pages (File size: 217K) |
| Chip Manufacturer | SAMSUNG |
TNAL0201
UtRAM USAGE AND TIMING
Figure 3.
toggle CS to high every 4µs
Over 4
µs
tRC
CS
WE
Address
Write operation has similar restriction to Read operation. If your
system has a timing which sustains invalid states over
4
µs
at
write mode and has continuous write signals with length of Min.
tWC over
4
µs
like Figure 4, you must toggle WE once to high
Figure 4.
Over 4
µs
and make it stay high at least for tRC every
4
µs
or toggle CS
once to high for about tRC.
CS
tWP
WE
Address
tWC
Figure 5.
toggle WE to high and make it stay high at least for tRC every 4µs
Over 4
µs
CS
tWP
WE
Address
tWC
tRC
Figure 6.
Over 4
µs
toggle CS to high every 4µs
CS
tWP
tRC
WE
Address
tWC
SRAM PLANNING
LIM-020311
SAMSUNG Electronics CO., LTD. reserves the right to change products or specifications without notice.
©2002
SAMSUNG Electronics CO., LTD.
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