K1S1616B5M-EE70T
| Model | K1S1616B5M-EE70T |
| Description | DRAM |
| PDF file | Total 12 pages (File size: 217K) |
| Chip Manufacturer | SAMSUNG |
Advance
K1S1616B5M
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, ZZ=WE=V
IH
, UB or/and LB=V
IL
)
t
RC
Address
t
OH
Data Out
Previous Data Valid
t
AA
Data Valid
UtRAM
TIMING WAVEFORM OF READ CYCLE(2)
(ZZ=WE=V
IH
)
t
RC1
Address
t
AA
t
RC2
CS
t
CO
t
HZ
t
BA
UB, LB
t
BHZ
t
OE
OE
t
LZ
t
OLZ
t
BLZ
Data Valid
t
OHZ
t
OH
Data out
(READ CYCLE)
High-Z
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
3. The minimum read cycle(
t
RC
) is determined by longer one of
t
RC1
and
t
RC2.
4. t
OE
(max) is met only when
OE
becomes enabled after t
AA
(max).
-6-
Revision 0.0
May 2002
