Class D audio with -111.2dB THD+N and 120.9dB dynamic range

That said, Delft University of Technology, in collaboration with Goodix Technology, appears to have achieved high fidelity figures of 120.9dB dynamic range and -111.2dB peak THD+N with the 0.18μm BCD prototype IC.

    At full power (10% THD), it can deliver 13W to 8Ω at 90% efficiency, or 23W to 4Ω at 86% efficiency.
    Ironically, despite the digital input, it has a deep-seated recourse to analog signals.
   
   On the front end, the capacitive DAC is used to avoid the thermal and 1/f noise that occurs with current control or resistive DACs.

    This drives a closed-loop Class D amplifier based on a capacitively coupled chopper amplifier topology.
    Since the DAC output contains DAC images around multiples of the sampling frequency as well as shaping quantization noise, care needs to be taken with frequency planning to prevent intermodulation between the DAC output and various chopper and PWM tones.
    The 24-bit input is upsampled to 768 kHz (16 x 48 kHz), reduced to 8 bits by a digital ΔΣ modulator, and then converted by the DAC to an analog signal for use in the chopper amplifier and the rest of the Class D amplifier, which has a 4.992 MHz three-stage PWM output running from the 14.4 V rail. This frequency is the 13th harmonic of the chopper frequency (and therefore odd), avoiding intermodulation of the sidebands.
    "However, this also means that the PWM frequency does not lie at a multiple of the sampling frequency [it is 6.5x], so some quantization noise folding occurs," Delft said. "Fortunately, the quantization noise around the PWM frequency is attenuated by the sinc roll-off and low-pass characteristics of the DAC spectrum, so the folding noise is negligible."
    The prototype is 7.5mm 2 with an interpolation filter and digital ΔΣ modulator in a separate FPGA.
    High Dynamic Range Op Amps Using Chopper Amplifiers
    The next paper at the ISSCC conference, also authored by Delft University of Technology, delves into the use of chopper amplifiers in high dynamic range operational amplifiers due to the fact that the input and output switches are switched simultaneously while the signal takes a limited amount of time to pass through the amplifier.
    This can lead to a slight error in the chopping time of the output, resulting in a spike-like output error.
    Using two parallel chopper amplifiers, chopping orthogonally and alternately selecting their outputs away from the chopping moment, can eliminate these spikes.
    Delft used a raw-quality chopper amplifier and then used the parallel amplifier only briefly around the chopping point of the main amplifier, allowing the 1/f noise and offset specifications of the parallel amplifier to be relaxed without degrading the overall quality, and allowing the secondary amplifier to be turned off most of the time to save power.
    The team used a 0.18μm BCD process to build the amplifier on 0.57mm 2 and consumed 620μA at 5V, dropping to 530μA with the secondary amplifier selected.
    With the op-amp connected as a buffer, a single 1Vrms 79kHz (~4x Fchop) input causes a -125.7dB IMD tone at 1kHz (4xFchop - Fin), which would be worse at -102dB if the main amplifier was used 100% of the time.
    The figure at 39kHz Fin (~2x Fchop) is -128.5dB, deteriorating to 112.8dB.
    At Fin <5kHz, the IMD tone is below -140dB background noise.
    The input current is 22.6pA.
    ISSCC 2023 Paper 3.1 A 120.9dB DR, -111.2dB THD+N Digital Input Capacitor-Coupled Chopper Class D Audio Amplifier
    ISSCC 2023 Paper 3.2 Chopper Stabilized Amplifier with Relaxation Fill Technique and 22.6pA Input Current
    The IEEE International Solid-State Circuits Conference, held annually in San Francisco, is a world showcase for IC-based analog, digital, and RF circuits. It provides an opportunity for IC and circuit design engineers to stay current with the technology and make connections.