Packaging Trend of Circuits in Portable Electronic Products

Summary: This paper describes the packaging trend of portable electronic products. The trend is that MCM packages using chip-level product circuits include SIP and 3D packages. These chip-level products can be mounted in packages in the form of FC or COB.

Keywords: Portable electronic products; Chip-level products; Multi-chip module; encapsulation

1 Introduction

IC packaging provides a satisfactory electrical, mechanical and thermal performance environment for integrated circuit chips through a series of processes and methods. For encapsulated devices, they are called modules. With the development of packaging technology, the concept of MCM (Multichip Module) has emerged. A multi-chip module is an electronic component or system in which several bare chips and some passive components are installed in a single package. In the mid-1990s, MCM technology was once considered as packaging technology, which can meet the needs of the growing electronic industry and has high added value. However, due to the high cost of MCM production, it has not been widely used, but only in some environmentally demanding and less cost-effective situations (such as aerospace, military research and other fields).

The emergence of Die products has opened the way for the large-scale application of MCM technology. In the portable system (such as notebook computer, mobile phone, etc.) and palm system (such as PDA, XBOX, etc.), in order to make the system have more functions and at the same time have the characteristics of small, light, thin and high reliability, the advantages of MCM assembly technology using chip-level products have gradually emerged. MCM with chip-level products is cheaper than traditional SMD (surface mounted devices). Compared with today's advanced SOC (on-chip system), it greatly shortens the product development cycle, thus winning the time to market.

Chip-level products (non-encapsulated and wafer-level encapsulated products) are terms describing IC devices. They are truly "chip size" encapsulations. WLP (wafer-level packaging), traditional COB (on-board chip) and inverted chip (FC) devices can all be chip-level products. Chip-level products can now appear on the market via encapsulated IC.

Advantages of 2-chip products

In today's information age, more and more electronic devices are used in automobiles, computers, communications, entertainment and other fields. In these applications, people have more and more requirements for the function and performance of electronic devices. At the same time, they also want products with smaller size, lighter weight, more affordable price and higher reliability. This requires electronic devices to develop in the direction of multifunction, high performance, miniaturization and lightweight. Using a chip-level product is an option to meet these requirements because it has the following advantages:

(1) Smaller size

On the interconnect substrates, using bare chips or WLP packaging chips makes it easy to obtain the least space occupied. We know that one of the important indicators to measure the advanced packaging technology is the ratio of the chip area to the area occupied by the chip on the base, also known as the "packaging efficiency" (Peff). People always want to achieve higher packaging efficiency. For cellular phones, the packaging efficiency was 0.17 before 2000 and has risen to 0.27 in recent years. With the application of chip-level products, especially 3D products assembled with chip-level products, the packaging efficiency of portable electronic products will be greatly improved.

(2) Excellent performance

With chip-level products, the interconnect length of the chip can be reduced, the interconnect delay can be reduced, and the influence of parasitic elements (such as parasitic inductance, capacitance, etc.) can be reduced, thus the electrical performance of the I/O end of the chip can be enhanced.

(3) Opportunities

At present, chip-level products have been widely used in the mass production of handheld and wireless systems, and the advantage of cost-effectiveness will further promote the application of chip-level products in more new fields.

(4) Price advantage

Smaller base plate size, simpler assembly process and faster time to market of new products can further reduce the cost of system solutions.

(5) Reliability

Provides higher quality and reliable products while meeting the expected cost performance ratio of consumers. At present, chip-level product equipment vendors have developed some powerful testing tools, such as chip and wafer-level test aging high-performance carriers, probe cards, etc. These tools can be used by chip-level product vendors to test and filter their products more rigorously, which greatly improves the reliability of the products they provide to meet the application requirements.

3 Packaging Trend of Circuits for Portable Electronic Products

3.1 COB (on-board chip) packaging

The so-called COB means that bare chips are adhered to the interconnect substrates with conductive or non-conductive adhesives, and then bonded by leads to achieve their electrical connection. If the bare chip is exposed to air directly, it is susceptible to contamination or man-made damage, which affects or destroys the function of the chip, then the chip and bonding lead are enclosed with adhesive. It is also called soft envelope (Fig. 1).

COB technology has been widely used in the production of electronic industry, especially in the production of some hybrid circuits and SMT assemblies that require lead bonding. Its advantage is that some post-processing operations are omitted, which reduces the cost of the product. In addition, it has a higher packaging efficiency (usually > 0.27).

In the electronic product market, COB occupies a large market share. However, in traditional COBs, the reliability is low because the chips used are test-free or conventional wafer test-free. In portable electronic products, chip-level products that have been rigorously tested and filtered can be used to achieve the reliability level of using conventional IC. COB, a traditional packaging technology, will play an important role in the packaging of portable products.

3.2 FC (flip chip) packaging

Direct chip mounting is the method by which interconnect terminals (I/O ports) of integrated circuits and interconnect substrates are used to achieve both chip adhesion and electrical performance interconnection. When mounted, the chip faces (bottom) the baseboard, which is also called FC (flip chip). Some new and emerging FC installation technologies are providing good benefits to the packaging industry.

During FC installation, the chip face down (the base plate) is mounted directly on the base plate through precise alignment. Inverted sheets are now mainly divided into reflow FC and adhesive FC.

3.2.1 reflow FC

In the 1960s, IBM started using solder ball bump chips installed with reflux soldering technology. IBM's solder ball bump process, called C4, uses high melting point lead-tin solder balls and therefore cannot be used for direct reflux soldering with wiring substrates such as FR4 at low glass transition temperatures. However, this bump can be used as a fixed support and can be directly refluxed with a thin eutectic lead solder on the surface of the bonding pad of the interconnected substrate. Another method is to fabricate eutectic solder balls on the chip, and then directly use the reflux soldering technology to connect with the base plate bonding pads.

3.2.2 Adhesion to FC

There are several ways to adhere FC in common use: 1. IC with solder ball bumps made by insulated adhesive film is directly adhered to printed circuit boards with narrow spacing interconnects. The adhesive film is suitable for high density I/O interconnection because of its good insulation performance. At the same time, the adhesive film also acts as a protective film and a sealing or underfilling material, and can alleviate the thermal stress between layers, which improves the reliability of the encapsulated product; 2. Another type of adhesive FC is to use anisotropic conductive materials (adhesive membranes or pastes) to achieve mechanical and electrical interconnection between the chip and the substrate. Anisotropic conductive film (ACF) is like paper (similar to double-sided tape), which consists of thermosetting adhesives, conductive particles and release membranes. Anisotropic conductive adhesives (ACA) plaster, consisting of thermosetting adhesives and conductive particles. Diagram 2 shows an anisotropic conductive material adhering to IC.

Adhesive FC has more advantages than reflow FC. First, the bond pad spacing of FC bonding can be smaller than that of reflux FC bonding. Second, the process of applying solder or flux is eliminated. Cleaning with FC is also much easier and does not use lead. In adhering FC, the bumps on the chip can be those formed by thermoacoustic golden ball bonding, which makes it easier to make the bumps on the chip in FC.

In FC, inverted chips provide more I/O terminals (inverted chips are usually arranged in arrays) because they can be used to fabricate I/O terminals on the whole chip surface instead of using the periphery of the chips as traditional wired circuits do. The internal I/O interconnection of the chip is shorter than that of the peripheral I/O, and the connection between the I/O end of the chip and the baseboard is shorter at the time of assembly, which reduces the loss of signal transmission and speeds up the operation of the chip. In addition, its relatively loose foot spacing is also conducive to chip assembly.

The I/O terminal number of FC and the ability of wire welded IC (peripheral pad placement) are compared as shown in Figure 3. From Figure 3, we can clearly see that the enormous difference between I/O terminals can be utilized when FC and conventional wire bonded IC chips have the same pad spacing. Another thing we should also see is that the characteristic size of IC still follows Moore's law and decreases year by year. Therefore, the ratio of the length of the chip periphery to the number of I/O terminals of the circuit will be reduced accordingly. For some IC chips, there may be problems when using peripheral pad placement. With a polygon array I/O structure, the number of I/Os may not be limited.

FC is widely used in portable electronic products. FC chips will be used more and more in portable electronic products due to its many advantages, high packaging efficiency (100%), good electrical performance and high reliability. Therefore, in the future of portable electronic products, FC production technology and installation technology need to be used extensively.

3.3 WLP (wafer-level packaging)

WLP, which performs tests on a wafer (chip-level product testing) and fabricates interconnect bumps, then cuts the wafer into individual pieces. The IC of WLP can be directly applied to surface assembly, which reduces manufacturing costs and accelerates the time to market of products. WLP has wider pin spacing and larger ball size than FC technology. Large spacing makes surface mounting easier. With large ball size and high mechanical strength, the stress per unit area of the ball is less due to mismatch of thermal expansion coefficient between IC chip and substrate. The high height of the solder ball can reduce the strain in the interconnect structure, that is, the deformation of the solder ball can be reduced, which can further improve the reliability of the circuit assembly. Table 1 compares some key parameters in WLP with FC.

WLP, which was developed from the CSP technology that rose in the late 1990s. In WLP, the area occupied by PCB assembly is slightly larger than the size of the chip. Its I/O end is on the surface of the chip and is compatible with traditional SMT processes. Because of the large I/O port spacing of WLP, it is easier to test and assemble, which reduces the difficulty and cost of testing and assembly. As it is possible to avoid underfilling when using WLP, it is more conducive to the wide application of WLP technology. However, there is less protection with underfill. If the structure is poorly designed, mismatching thermal expansion coefficients between the chip and the substrate may result in excessive thermal stress or unknown external forces that may damage the device. Therefore, in the design of WLP, attention should be paid to increasing the stress buffer layer, controlling the geometry size of the welded ball and optimizing the placement design of the welded ball, so as to increase the reliability of the welding. In addition, because the chip size of the wafer-level packaging is generally small and the mechanical shear stress produced by thermal expansion mismatch is small, the possibility of circuit failure due to thermal expansion mismatch is small, so the risk of use is small, so that WLP can be further promoted and applied.

The packaging efficiency of WLP circuit is close to 100%, the thickness of the package is thin, and the reliability is equivalent to that of conventional IC. WLP circuits will be used more and more in the assembly of portable electronic products to replace conventional packaging IC. Therefore, more and more WLP manufacturing technology and WLP circuit installation technology will be used in the packaging of portable electronic products.

3.4 MCM (Multichip Module) Packaging

MCMs are usually fully customized, with dozens or hundreds of components mounted on a large, high-density substrate. Because of the large number of components, the processing process is more complex. Rework is more difficult if there is component damage in the module. In addition, after the module is assembled, there is an early failure of the components in the module, so it is very costly. Traditional MCM technology is mainly used in military research and high performance computer technology. With the advent of chip-level products, the advantages of MCM technology emerge. Chip-level products can be used in the assembly of portable electronic products, which greatly improves the qualification rate of MCM assembly and alleviates the early failure of components.

The advantages of multichip packaging are as follows:

Chips of different wafer or process technologies can be assembled in the same package body.

(2) Compared with SOC, MCM can shorten the time to market and reduce the investment risk;

(3) electromechanical (micro-mechanical) systems, photoelectric and display elements can also be integrated in one package;

(4) Different encapsulation techniques can be used to encapsulate various components together;

Packaging efficiency can be improved, chip assembly materials can be saved, and test methods can be simplified, thus reducing packaging costs. Because of these advantages, MCM technology has been applied in portable electronic products. In the future, MCM packaging technology will become a very important packaging technology in the packaging of portable electronic products.

3.5 SIP (System Encapsulation)

The concept of system encapsulation emerged in the 1990s. It encapsulates different types of devices in a tube and shell to form a complete system. Its encapsulation shape is the same as that of a standard single chip encapsulation, so it is called system encapsulation. For example, in portable electrical appliances, microprocessors, memory, graphics cards, etc. are placed on a high-density low-value interconnected substrate and packaged to form a system. SIP is a kind of packaging belonging to MCM. It usually contains several chips (generally less than 5) and some passive components. The system packaging is easy to assemble because it has the same shape as single chip circuit packaging, such as BGA.

SIP has the following advantages:

Chips with different structures and fabrication processes can be integrated and encapsulated in one shell at a minimum cost. For example, in the design of memory devices, multiple memory chips can be assembled together. This can shorten the product design time, increase the design flexibility, and quicken the time to market of products, thus gaining economic benefits, compared with SOC technology in which multiple memory chips are embedded in one chip.

(2) Passive elements, antennas, filters, shielding elements can be integrated into a single package, thus reducing the parasitic effect between devices, improving the shielding effect, and improving the device performance;

(3) Because SIP technology is integrated by components, it can modify the design according to the different needs of customers, which greatly increases the design adaptability, and also can quickly meet the market demand. Because of these advantages, SIP is widely used in portable products. In the future, SIP devices will be used more and more in portable electronic products.

3.6 3D (3-D) packaging

With the market's "harsh" requirements for products: light, thin, short, small, highly integrated, high performance and high reliability, a new type of packaging is becoming familiar with people, which is 3D packaging. 3D packaging can also be thought of as SIP. Due to the maturity of chip-level product technology, 3D technology has been widely used in cellular phone assembly since 1999. It uses stack method to overlap Flash memory and static random memory (SRAM) chips and encapsulate them in a single shell to achieve larger storage capacity, thus greatly improving the packaging efficiency. For packaging efficiency, the efficiency of bare chips is 100%, WLP is close to 100%, and CSPs using 3D stack packaging can exceed 100%, or even several times (if stacking with multiple chips). In 3D packaging, multi-layer film technology is introduced along with the improvement of packaging efficiency. They are stacked together using wafer thinning, ultra-thin adhesion, low radian lead bonding and thin thickness encapsulation technology or FC mode, which makes the product thickness after multi-chip stacking comparable to that of traditional single-chip devices, thus making 3D packaging more competitive in the market. 3D stack packaging is not limited by the kind of devices. Chips with the same or different sizes and devices of the same or different types can be stacked together. In addition to IC devices, separation devices and passive components can also be stacked together. After encapsulation, a high performance functional block in the form of a complete SIP is formed.

There are six basic forms of 3D packaging:

1. Stack after packaging is complete:

(2) Lead bonding method;

(3) Inverted chip mode;

(4) The combination of Silicon-on-Silicon;

3-D packaging of folded sheet shape

Mixed type.

Although 3D packaging can effectively improve packaging efficiency and preliminary integration of the system, its complex structure, thermal design, electrical properties, warping, reliability control and combined crystal yield are more challenging than single chip packaging. However, with the progress of technology, 3D packaging technology will have a bright future in the packaging of portable electronic products.

4 Concluding remarks

In the 1990s, MCM technology only played a role in the aerospace industry and high-performance computer field, mainly because it was too expensive. Today, with the advent of chip-level products, the advantages of MCM packaging technology have emerged, which can be widely used in the production of portable electronic products. In MCM assembly, chip-level products can be used for COB packaging, FC packaging, WLP chip packaging. It can be encapsulated in either traditional MCM or SIP or 3D.

With the development of science and technology, the applications of IC products are growing at an alarming rate, and packaging types supporting various products are emerging to meet people's "stringent" requirements for IC products. Packaging is no longer a simple protection IC, but also an important factor for system designers to ensure its product form and function. What will tomorrow's portable packaging look like? Let's wait.

(Article Source: China Grid)

Source:Xiang Xueqin