Digital Recording System Based on K9F6408U0A and SDS202A

Abstract: K9F6408U0A is a Non-large 64-megabit flash memory produced by Samsung Company. It has the advantages of low operating voltage, fast scratch speed and small size. Voice chips produced by SPDS202A Taiwan Sungyang Company. In this paper, the digital recording system based on SPDS202A is introduced, and the specific method to realize the copy function between two pieces of K9F6408U0A is also introduced. The related hardware interfaces and software programs are given.

Performance introduction of 1 K9F6408U0A

K9F6408U0A is a 44-foot surface encapsulation device. Its working voltage is 2.7-3.6A, which is especially suitable for the requirements of low power consumption and wide voltage of consumer electronics. It has (8M+256K) bit inside × Bit memory unit array, consisting of 16384 rows and 528 columns. It has a structure of 1024 blocks, 16 pages each, each with (8K+256) bytes, and can be used for page reading, writing, and block erasing. It contains a (512+16) byte data register that can be used for data conversion of storage units during page read and write operations. The advantage of K9F6408U0A is that its commands, data and addresses can communicate with the main controller through eight I/O ports. This greatly simplifies the connection of the system and enhances the stability of the system. In addition to the eight I/O ports, K9F6408U0A includes the following control lines, which make it easy for the system master controller to control K9F6408U0A. They are:

CLE: Command lock enabler, high level valid. At the rising edge of the WE signal, the command signal can be locked into the command register through the I/O port.

ALE: Address latch enables the power end, high level valid. At the rising edge of the WE signal, the address signal can be locked into the address register through the I/O port.

CE: Slice selection, low level effective. High CE levels are ignored during page programming or block erase operations or when the device is busy.

WE: Write enabler, commands, addresses, and data are locked at the rising edge of the WE signal.

RE: Read enabled port, where data is sent to the I/O port along the descending edge of the port, and the internal column address register is increased by 1.

WP: Write port, low level effective. Programming and erasing operations are prohibited when this is low.

R/B: Operational status indicator. When low, it means that you are programming, erasing, or reading, and it gets higher after the operation is finished.

Introduction to 2 SPDS202A

SPDS202A is a very cost-effective voice chip produced by Taiwan SUNPLUS company. It can easily interface with the host to control voice chip recording, playback and other functions by issuing command codes. It has the following characteristics:

Separate audio/speech codec/decoder chips, using SACM-S480 or SACM-S3200 compression and decompression algorithms. It has a sampling rate of 8 kHz and a data low code rate of 4.8 Kbps or 32 kbps.

With digital volume control function;

With FLASH management function, FLASH data can be automatically managed internally. The standard FLASH interface can connect up to 4 FLASH slices, totaling 64Mbit.

The UART interface makes it easy to interface with PC and other RS232 devices, and to upload or download data easily.

Embedded phase-locked loop circuit;

High quality 10-bit 8kHz ADC and DAC are embedded;

Low power consumption, 2.8V~3.6V operating voltage.

Because of the above features of SPDS202A, only a few additional peripheral circuits are needed to form a large-capacity voice recording system.

3 Composition of digital recording system

The structure of digital recording system with SPDS202A and W78E58 as its main controller is shown in Fig. 1. W78E58 is compatible with MCS-51 series single-chip computers. Its built-in 32 kflash EEPROM can be used as program memory, while the built-in 256-byte SRAM is suitable for the magnetic programming operation of K9F6408U0A.

Figure 2 shows the hardware interface circuit of W78E58 and SDS202A. In the diagram, TADCE is a chip selector signal line on which latch commands/data can be raised. TADSEL1 and TADSEL0 are command selection signal lines whose functions are listed in Table 1.

Table 1 Commands Select Signal Line Functions

TADD7-TADD0 is an 8-bit data line. When it works, the SPDS202A of the master controller sends three bytes of data, of which one byte is always 0FFh, the second is a low byte of the command code, and the third is a high byte of the command code. The primary controller then receives two bytes of data returned from SPDS202A. The communication procedure between them is as follows (written in C51):

Void Mcu_ 202_ Comm(void) /*MUC and SDS202A communication program*/

{via=0xFF;/*bytes to 0FFh*/

SendOneData();/* Invoke Send One Byte Data Subprogram*/

Via=CMDL;/* Second Byte Send Command Code Low Byte*/

SendOneData ();

Via_ CMDH; /* Third Byte Send Command Code High Byte*/

SendOneData ();

ECHOL=ReadOneData(); /* Read Return Data*/

ECHOH=ReadOneData();

}

The following is an example of how the system works by taking the implementation of the recording function as an example.

Void Record (void)

{CMDL=0x00;/*Send Audio Command Code*/

CMDH=0x10;

Mcu_ 202_ Comm ();

If (Err=1) /* If an error occurs, return */

{Err=0;

Return;

}

}

It can be seen that the system achieves its functions by sending a series of control command codes to SPDS202A through the main controller.

4 Implementation of Replication Function

In order to be able to save and back up the recorded information, one copy function should be considered, that is, to completely copy one piece of information on K9F6408U0A to another. The hardware interface circuit to achieve this function is shown in Figure 3. In the figure, two pieces of K9F6408U0A signal lines are multiplexed except that the slice selection is separated. Replication can be achieved using the following programs:

Void Copy (void)

{FCEB2=1;

FCEB1=0; /* Selected FLASH*/

For (RowAdd2=0; RowAdd2< 64; RowAdd2++)

{for (RowAdd1=0; RowAdd1< 256; RowAdd1++)

{BlockErase ();} /* Call the block erase subfunction to erase the FLASH content of the slice*/

}

For (F1RowAdd2=0, F2RowAdd2=0; (F1RowAdd2< 64)

&& Amp; (F2RowAdd2< 64); F1RowAdd2++,

F2RowAdd2++)

For(F1RowAdd1=0, F2RowAdd1=0;

(F1RowAdd1<256) && Amp; (F2RowAdd2< 256);

F1RowAdd1++, F2RowAdd1++)

For(F1ColAdd=0, F2ColAdd=0; (F1ColAdd<256)&& Amp; (F2ColAdd< 256); F1ColAdd=F1COAdd+128; F2ColAdd=F2ColAdd+128)

{CE1=1;

CE2=0;

SetPointer=0x00;

F1RdData(); /* Call read data subfunction from slice FLASH*/

CE2=1;

CE1=0;

SendData(); /* Call the send data subfunction to the second FLASH page register*/

CE1=1;

CE2=0;

SetPointer=0x01;/* Set the page register pointer to the second half of the page register*/

F1RdData ();

CE1=1;

CE2=0;

SendData ();

FwrData(); /* Execute page programming commands to write data to the second FLASH*/

}

}

}

}

5 Concluding remarks

With this digital recording system consisting of a voice chip and a capacity FLASH, you can record up to 3.7 hours of voice information on a 64Mbit FLASH. At the same time, in order to save the recorded information, the copy method described in this paper can also be used to make a copy between two pieces of FLASH. The system can be widely used in situations where long-term voice recording is required.

Reference:

[1].RS232 Datasheethttp://www.dzsc.com/datasheet/RS232_585128.html.
[2].W78E58datasheethttp://www.dzsc.com/datasheet/W78E58_705395.html.
[3].MCS-51datasheethttp://www.dzsc.com/datasheet/MCS-51_477840.html.