Abstract: A four-channel intelligent arbitrary wave generator and waveform modulation module based on VXI bus are introduced. This module uses DSP+GA to achieve intelligent control, and uses advanced DDS (Direct Digital Frequency Synthesizer) technology to generate arbitrary waves. The output waveform can be loaded for wave modulation. This module has four independent channels, which are electrically isolated from each other, and can output continuously adjustable voltage and current signals.
Key word:VXI DDS Arbitrary Wave Generator Modulation
VXI bus is the abbreviation of VMEbus extensions for Instrumentation. The VXI host box has 13 slots, of which the zero slot controller is the administrator of the system. The VXI module can be divided into four types, register base, message base, memory and extension module, according to its nature, characteristics and supported communication rules. Each module has three types of address spaces: A16, A16/A24, and 116/A32.
This paper introduces a module with arbitrary wave generation and AM function using DDS (Direct Digital Frequency Synthesizer) technology. Compared with traditional frequency synthesis technology, DDS technology has many advantages: short frequency switching time, wide operating frequency range, high frequency resolution, continuous phase change and easy to modulate the output signal. Some companies have introduced a variety of DDS chips, which provide great convenience for circuit design, but can not meet all the requirements. For example, when implementing complex functions such as FM and AM, it is very inconvenient to use existing DDS chips. Using programmable logic device (CPLD) or field programmable gate array (field programmable gate array (field programmable gate array) to implement DDS has great flexibility and can meet the requirements of circuit design very well.
Basic principles of 1 DDS
DDS is shown in the basic schematic diagram in Figure 1. It mainly consists of standard reference frequency source, phase accumulator, waveform memory, digital/analog converter, low-pass smoothing filter, etc. The reference frequency source is generally a crystal oscillator with high stability, and its output signal is used to synchronize all parts of DDS. The essence of DDS is to sample phases at controllable equal intervals.
The structure of the phase accumulator is shown in Figure 2. It is a DDS implementation consisting of an N-bit word length adder and an N-bit phase register sampled by a fixed clock pulse. The output of the phase register and the frequency control word K of the external input are used as the input of the adder. When the clock pulse arrives, the phase register samples the sum of the value of the phase adder and the frequency control word K of the previous clock cycle as the output of the phase accumulator at this time. The high M-bit output of the phase accumulator is used as the address of the waveform memory query table, and the corresponding amplitude values are read from the waveform memory and sent to the digital/analog converter.
When the DDS is working normally, under the control of the standard reference frequency source, the phase accumulator continuously performs phase linear accumulator (each time the accumulator is the frequency control word K), which will overflow when the phase accumulator is full, thus completing a periodic action, which is the frequency cycle of the DDS synthetic signal. The frequency of the output signal waveform is:
Clearly, when K=1, the minimum frequency is output, that is, the frequency resolution is fmin=fc/2N. In formula, fout is the output signal frequency; K is the frequency control word; N is the word length of the phase accumulator; FC is the operating frequency of the standard reference frequency source.
2 Realization of Waveform Generator Module
2.1 Hardware section
The block diagram of the waveform generator module is shown in Figure 3.
The hardware can be divided into bus interface, DSP and logic control circuit, four-channel DDS waveform generation and modulation circuit, signal conditioning and output interface. Among them, dual-port RAM is used as communication medium between zero-slot controller and DSP, and IDT709289L is used for dual-port RAM with 64K capacity. × 16Bit.
According to the characteristics of zero slot controller and module exchanging information, this module uses A16/A24 operation mode of register base with data of 16Bit. In addressing mode A16, each module has a set of configuration registers that the system can access to obtain device type, model, manufacturer, address space and memory requirements. In A24 mode, the zero slot controller can configure a module's storage space of 256n × 223-m, where n is 1 in A32 mode, 0 in A24 mode, and M is the value defined for the four-digit height of the device model register. In this module, the m value is 6 and the memory address space is 128Kbyte. The bus interface is implemented by EPM3256A from ALTERA. The in-board interface logic and all control logic are implemented using Verilog hardware description language.
Dual-port RAM in interface circuit is used as command, parameter and data transmission, which is divided into command parameter area and data area. Dual-port RAM is divided into 16 pages, each of which is 4K × 16Bit, the first 15 pages as a custom waveform transport area, and the 16th page as a command parameter area. The use of dual-port RAM makes the module design independent of the VXI system, which enables the waveform generation circuit to be easily ported to other buses.
TI's TMS320F206 is selected as the in-board master CPU chip. It mainly plays an intelligent control role, receives various commands sent through the VXI bus, then analyzes the commands, executes the commands, and coordinates the work of each part of the module. Compared with the non-intelligent module, this module has obvious advantages. In addition to custom waveforms, the zero-slot controller only needs to issue simple commands and parameters to the module, and the DSP can complete all the functions. This greatly reduces the time overhead of the upper machine and the controller, allows them more time to handle other events, and helps to ensure that the entire VXI system works reliably and coordinately.
The DSP Extended Data Memory consists of one IDT709289L and four IDT7025S. Each page of IDT9289L is mapped to 0x7000~0x7FFF of the DSP data area. It is used for interface circuit and the page switch is controlled by I/O decoding of the DSP. Four IDT7025S are mapped to the data area 0x8000~0x9FFF of the DSP. They are used as four-way DDS waveform memory, and four IDT7025S are controlled by the DSP. The decoding and control circuit related to DSP is implemented by a piece of EP1K10.
Figure 3
The function block diagram of DDS waveform generation and output for a single channel is shown in Figure 4.
Each channel's accumulator and logic control circuit uses a piece of EP1K30, which is used to implement the accumulator and step control word register and complete functions such as address decoding on board, two-stage DAC control, waveform jitter compensation and relay control of this channel. The accumulator is 32 bits long and the clock reference source frequency is twice the output frequency of the DSP. Level II DAC is used to generate waveforms, Level II DAC is used to control the output amplitude and the forward and reverse phases of waveforms, and the Level II DAC output is smoothed and amplified.
According to the performance requirements of the system, the output uses a voltage isolation amplifier, which is isolated from the bus and has four independent channels. This module has a total of one digital and four analog output sites. In this way, not only the VXI system and other channels can be secured, but also the module load and the mutual interference of the VXI system can be reduced.
The waveform data memory IDT7025S is divided into two equal pages A and B, which can achieve jitter-free switching between different waveforms, each page being 4K × 16bit. When the DDS starts working, the DSP pioneer home page A writes the waveform data and generates the waveform under the control of the DSP. When switching to another waveform, simply write the data of another waveform to Page B and switch the address (12 bits high) generated by the 32-bit accumulator to Page B. In this way, waveforms with continuous amplitude and phase can be switched without dithering.
Each channel uses two levels of 12Bit DAC, which are set to bipolar voltage output. The reference voltage source for Level 2 DAC can be an internal reference or an external carrier, and the reference voltage source for Level 2 DAC can be an internal reference, an external carrier or a level DAC voltage output. By not setting the reference voltage source to which two levels of DAC are connected (switching by relay), the following functions can be achieved respectively:
(1) For direct output, the reference voltage source of the second DAC connects to the internal base station. The second DAC voltage output is: V2out=(Din2-2048)/212, which can control the DC output amplitude and positive and negative polarity by entering different Din2.
(2) As a function generator, the level DAC reference voltage source connects the internal base, the level 2 DAC reference voltage source connects the level DAC voltage output, and the waveform memory stores different function waveform data to output different function waveforms. In this case, the output voltage of stage DAC is: V1out=Vref × (Din1-2048)/212, where Vlout is the level DAC bi-directional output voltage, Vref is the DAC reference voltage source, and Dinl is the level DAC input data. Here the Vref is constant 2V, only Dinl is variable, Din1 corresponds to 4096 waveform amplitude data in waveform memory (one cycle). When the waveform data is loaded into the DAC in turn at a rate of 500 kHz, the frequency of the output waveform of the DAC obtained from formula (1) is: fout=K × (106/2 33). The second DAC output voltage is: V2out=Vlout × (Din2-2048)/212, where V2out is the second DAC output voltage and Din2 is the second DAC input data.
(3) As a custom waveform generator, the level DAC and the second level DAC are set to (2). The difference is the content of the waveform memory. Zero slot controllers write custom waveform data to the first 15 pages of dual-port RAM (IDT709289L) according to a certain protocol. DSP also takes out the data according to a certain protocol and sends it to IDT7025S, IDT7025S A and B pages of the specified channel for alternate switching to connect the output custom waveform.
(4) External load wave modulation, level DAC reference voltage source connected with external carrier, Level 2 DAC reference voltage source connected with DAC voltage output. The external loading wave is a sinusoidal signal Vsin. α X+ θ) , Where V is the carrier voltage value, α Is the coefficient of the independent variable x, θ Is the initial phase. Level DAC voltage output is: Vlout=Vsin( α X+ θ) × Dinl/2 12, which implements carrier amplitude modulation. The second DAC is used to control the entire amplitude with the output voltage V2out=Vsin( α X+ θ) × Din1/2 12 × (Din2-2048)/ 212, Din2 is the input data for the second-level DAC.
(5) Direct carrier output, only the reference voltage source of the second DAC is connected to the external carrier, and the second DAC voltage output is: V2out=Vsin( α X+ θ) × (Din2-2048)/212.
Because the isolation amplifier has some output noise, the signal amplifier is placed before the isolation amplifier and the low-pass filter is placed after the isolation amplifier. This avoids amplifying the noise isolated into the amplifier and smooths the filter effectively.
The voltage output is amplified by the power amplifier OPA445, which achieves (+) 12V output. The current output is achieved by the voltage/current converter AD694, and the current output range is 0-20mA or 4-20mA.
2.2 Software Section
The software mainly consists of two parts: DSP program and VXI system host bottom driver function and test program.
The DSP program is mixed with C language and assembly language. The program of control part uses assembly language, which improves the efficiency of the program. The data generation part uses C language which is relatively simple to implement, avoiding complex programming using assembly to process data.
The PC test program is compiled with LabWindows/CVI of NI Company. LabWindows/CVI is a C-based programming environment with rich user interface controls and VXI bus system functions, which makes programming simple and convenient. The module-oriented operation functions are packaged to generate a.Dll file that can be called by the system.
3 Result of implementation and analysis
Figure 5 shows the output waveforms of square, serrated, sinusoidal and triangular waves with an output frequency of 10 kHz, with peak-to-peak values of 24V. Figure 6 shows the modulation wave output waveform, with 10 kHz external sine wave as carrier signal, 1 kHz sine wave as modulation signal, and peak-peak value of 24V. Figures 5 and 6 are sampled from Tektronix's TDS210 oscilloscope.
The experimental waveform output has a frequency resolution of about 0.1%, which is obviously larger than the theoretical frequency resolution of fmin=106/233=0.0001164Hz. After analysis, the system errors include: (1) phase truncation error; (2) Errors caused by interference caused by circuit board layout and wiring factors; (3) The error caused by the influence of the stability of the standard reference frequency source; (4) errors introduced by D/A converters; (5) Quantization error introduced by limited word length of waveform amplitude storage data.
The DDS implemented in this module has various advantages over traditional methods. Because of the powerful data processing ability and flexible control function of DSP, plus the high performance and high integration of FGPA, the module has excellent performance. In addition, this implementation of DDS has great flexibility to perform complex filter modulation.
Due to the inherent characteristics of DDS digitization, such as phase truncation of accumulator, quantization of waveform amplitude, and non-linearity of digital/analog converter, the output signal spectrum has a high spuriousness, which is especially prominent when the output frequency is high. Therefore, some improvement measures should be taken in the design process. For example, the structure of DDS is improved, the structure of waveform memory is optimized, the suitable digital/analog converter is selected, and the dithering injection technology is used to minimize its spurious, so that the DDS system has better performance.
