Design of CAN Bus Intelligent Node Based on ARM

CAN (Controller Area Network) is the controller local area network. CAN bus is one of the most widely used Fieldbus in the world. It was first introduced by Bosch Corporation in Germany. CAN communication protocol is a data communication protocol used between internal measurement and execution parts of automobiles.

As a kind of remote network communication control method with advanced technology, high reliability, perfect function and reasonable cost, CAN bus has been widely used in various automatic control systems. For example, in automotive electronics, automatic control, smart building, electronic system, security monitoring and other fields, CAN bus has incomparable advantages. This design gives CAN bus node scheme. It uses the built-in multi-channel CAN bus controller PLC2294 as the main controller, which makes the node small in size, low power consumption, good anti-jamming. Therefore, it is especially suitable for automotive, industrial control, medical system and fault-tolerant maintenance bus.

1 Hardware Design

Features of 1.1 LPC2294

ARM7 Series 32-bit embedded microprocessor with ARM7F4I core is currently a widely used embedded RISC processor. The chips are small in size, low in power consumption, low in cost, combination of high performance and flexibility, have more registers, and provide an expanded, fixed-growth 16/32-bit dual instruction set. Using 16-bit Thumb instructions can save up to 35% space. It also implements water injection line operation, provides embedded ICE2RT logic, supports on-fragment and debug point support, and has advanced software development and debugging environment.

The LPC22994 selected in this design is a powerful and ultra-low power 32-bit microcontroller with ARM7F4I core launched by PHILIPS. 144-foot encapsulation, two 32-bit timers, eight-way 10-bit ADC, four-way CAN and PWM channels, and up to nine external interrupts, with 256-Kbyte high-speed Flash memory and 16-Kbyte static RAM embedded internally, comprising 76 (using external memory) ~112 (monolithic) GPIO ports. Such abundant on-chip resources can fully meet the needs of general industrial control, while reducing the complexity of system hardware design. In addition, LPC2294 supports JTAG real-time simulation and tracking, 128-bit-wide memory interface and unique acceleration structure, enabling 32-bit code to run at operating frequencies up to 60MHz.

LPC2294 is internally integrated with four CAN controllers: CAN2.0B compliant with CAN specification, ISO 11989-1 standard: bus data baud degree can reach 1 Mbps; Access to 32-bit registers and RAM; Global acceptance filters recognize 11-bit and 29-bit Rx identifiers for almost all buses; The acceptance filter provides FullCAN-style automatic reception for the selected standard identifier.

As a part of this design, LPC2294 not only plays the role of a master controller, but also acts as a node controller of the CAN network, which implements data transmission and exchange with other nodes in the network.

1.2 CAN Node Hardware Circuit Composition

The hardware circuit of the CAN node is shown in Figure 1, which is composed of an ARM microcontroller LPC2294, a CAN bus transceiver TJA1050T, a high-speed optical coupling 6N137, and a power isolation module B0505S.

The crystal frequency range of the master chip LPC2294 is from 1 to 30MHz. This design chooses a crystal frequency of 20MHz, which can increase the CPU clock frequency by setting an internal VPB frequency divider. Internal 256K-byte high-speed Flash memory is used for code and data storage. For FLASH memory, system programming (ISP) or application programming (IAP) can be done through the built-in serial JTAG interface. In order to facilitate debugging and system upgrade, these interface circuits can be reserved in the design.

LPC2294 is powered by dual power supply. The power supply voltage of the CPU ranges from 1.65 to 1.95V (1.8V +8.3%) and I/O from 3.0 to 3.6V (3.3V +10%).

Transceiver TJA1050T is the interface between CAN protocol controller and physical bus. It is fully compatible with ISO 11898 standard. CANH and CANL work together perfectly to reduce electromagnetic radiation to a lower level. In addition, when TJA1050T is powered off, the bus is passive, which makes TJA1050T much better than previous CAN bus transceivers in performance. TJA1050T has two working modes: high speed mode and silent mode (they are controlled by pin "S"). In high-speed mode, the bus output signal has a fixed slope and switches as fast as possible. High-speed mode is suitable for bit-speed and bus length situations where the transmitter-receiver cycle delay is minimal. Transmitter is disabled in mute mode. It does not care about the input signal of TxD. Mute mode prevents network communication from jamming when the CAN controller is uncontrolled.

1.3 Anti-interference Design of Hardware

In the applications of this design, there are many devices that generate electromagnetic signals, including ultra-short wave devices, audio devices, power supply, etc. Therefore, anti-jamming equipment display is particularly important. The following measures have been taken:

(1) In order to further improve the anti-jamming capability of the CAN bus nodes and ensure that the nodes are completely isolated and independent electronically, the TX0 and RX0 of LPC2294 are connected with the RXD of TXD of TJA1050T through high-speed optical coupling 6N137, respectively. It should be noted, however, that the two power sources used in the optical coupling part of the circuit must be completely isolated, otherwise the use of optical coupling will be meaningless. Full isolation of power supply uses small power isolation module B0505S. Although the circuit is more complex, it improves the stability and security of the nodes.

(2) Two 120_resistors are added to the ends of the CAN bus, which play an important role in matching the bus impedance. Removing them will greatly reduce the anti-interference and reliability of data communication, even make it impossible to communicate.

(3) CANH and CANL are connected with two small capacitors of 30pF in parallel with the ground, which can filter out high frequency interference on the bus and have a certain ability to prevent electromagnetic radiation; A 5.6V TVS tube is incorporated between the two CAN bus access terminals. When the CAN bus breaks into the voltage interference, the short circuit of the TVS tube can provide a certain overvoltage protection.

(4) In order to reduce the field interference to the nodes, it is useful to shield the twisted pair, and according to practical experience, the shielding layer of the shielded cable does not need to be grounded.

2 Software Design

The software debugging environment uses ARM Core Processor Integrated Development Tool ADSv1.2 from ARM. ADSv1.2 integrates assembler, C+, C++ compiler and debugger, provides high compilation efficiency, provides a powerful system library, supports software debugging, JTAG emulation debugging and hardware debugging. This design uses JTAG simulation debugging.

For the general 32-bit ARM application system, the running environment must be initialized before running the main program, that is, writing the boot code for the ARM chip. This startup code includes exception vector table, stack initialization, storage system initialization and target board initialization, etc. It is generally written in assembly language. For this design, the key is to write CAN driver. The main program only needs to call the interface provided by the driver to receive and send data. The driver includes four parts: initialization of CAN controller, receiving data, sending data and bus exception handling. chart
2 is the main program flowchart.

2.1 CAN controller initialization

The operations to initialize the CAN controller include hardware enabling, software resetting, device alarm bounds, device bus baud rate, device interrupt working mode, device acceptance filter working mode, device working mode and starting CAN, etc. The initialization procedure is as follows:

HwEnCAN (CanEum); // Hardware enabled, CanNum=0-3, four-way CAN controller

SoftRstCAN (CanNum); // Software Reset Register

CANEWL (CanNum). Bits.EWL_ BIT=USE_ EWL_ LAN [CanNum]; // Set error warning bounds

CANBTR (CanNum). Word=USE_ BTR_ CAN[CanNum]; // Initialize baud rate

VICDefVectAddr=(UINT32) CANIntPrg; // Initialization interrupt is a non-vector interrupt

VICIntEnable 1=(1<<19)|(1<<(20+CanNum)|(1<<26+CanNum));

CANIER(CanNum). Word=USE_ INT_ CAL[CanNum];

CANAFMR.Bits.Accbp_ Bit=1; // Configure acceptance filters (bypass status, i.e., shielded acceptance filters)

CANMOD (CanNum). Bits.TPM_ BIT=USE_ TPM_ CAN[CanNum]; // Initialize working mode

CANMOD (CanNum). Bits.LOM_ BIT=USE_ MOD_ CAN[CanNum];

SoftEnCAN (CanNum); // Start CAN

The pin connection between the internal and external components of LPC2294 is controlled by the pin connection module. The hardware enablement of the CAN controller is to control the multi-switch through the software device GPIO register, connecting a specific pin to the CAN controller. Software reset is required before each CAN register of the device, because some registers of the CAN must be read and written in a soft reset state.

It is worth noting that LPC2294 provides global receive identifier queries for all CAN controllers. 2KRAM can hold 1024 standard identifiers or 512 extended identifiers or a mixture of both types. With software processing, 1-5 identifier tables can be set up in this RAM. Compared with the independent CAN controller SJA1000, it can filter any complex ID more easily and meet the receiving filtering requirements of complex IDs. This undoubtedly greatly reduces the complexity of system software design and the burden of running. To set how acceptance filters work, you must create a LUT table, specify the starting address of each table, and initialize the table with the actual ID address. Set acceptance filter mode registers. If the node does not actively send data, it can choose to enter sleep mode when the bus is inactive.

2.2 Data Sending

After packaging the data to be sent into a frame format that complies with the CAN protocol, it can be written to the sending slow station area and sent automatically. Figure 3 is a flowchart of the sending subprogram.

The status of the send buffer must be queried before it can be written. Each CAN controller in LPC2294 has three send buffers whose status can be known by querying the CANSR. Data is written only when there is space in the send buffer. This step is particularly important when sending large amounts of data, otherwise sending reliability cannot be guaranteed. After successful start-up send, data can only be successfully sent by querying the TCS bit of CANGSR or by configuring send success interrupt.

2.3 Data reception

Receiving data can be queried or interrupted. CAN bus is not always active for a certain period of time, so interrupt mode can be used to improve efficiency. You must be able to receive interrupts in the initializer. In the interrupt service subprogram, read the CANICR to determine if there is a receive interrupt flag, or read the receive buffer data. To prevent receiving buffer data overflow, a circular receiving data queue is created to temporarily store data, and the main program obtains bus data by querying the queue.

2.4 Exception handling

In the case of a serious failure of the online bus, the CAN node may be disconnected from the bus when the following register bits are positioned: the BS bit of the CANSR, the BEI bit of the CANIR, and the EI bit (if enabled) and the RAM bit of the CANMOD. RM resets and disables many CAN controller functions. Software must be set to zero RM bit next. Sending an error counter counts down the 128th thing of the bus release condition (11 consecutive implicit bits). The software can monitor the decreasing counter count by reading the Tx error counter.

In applications, if the data previously transmitted to the CAN controller is not read out and the receive buffer is not released in time, the latter information may be lost. The data overflow bits for CANSR must be cleared by writing the command register. Both exceptions can be handled by exception interrupts by adding processing code to the interrupt subprogram. Other bus exception handling can determine whether or not to be handled in the software based on usage.

In summary, software development and planning are important. ARM7F4I instruction set is RISC based and has 32-bit ARM/16-bit Thumb double-fingered SR calls to each other. Therefore, to increase program code density, some code that does not require high performance can be written using Thumb instruction sets.

Because of its small size, low power consumption and good anti-jamming performance, the scheme has been applied to a vehicle communication device with complex electromagnetic environment, which meets the requirements of the CAN network node of the project.

Reference:

[1].ARM7F4Idatasheethttp://www.dzsc.com/datasheet/ARM7TDMI_139812.html.
[2]. RISCdatasheethttp://www.dzsc.com/datasheet/RISC_1189725.html.
[3].TJA1050Tdatasheethttp://www.dzsc.com/datasheet/TJA1050T_649183.html.
[4].6N137datasheethttp://www.dzsc.com/datasheet/6N137_91364.html.
[5]. TVS Datasheethttp://www.dzsc.com/datasheet/TVS_1174166.html.
[6].SJA1000 Datasheethttp://www.dzsc.com/datasheet/SJA1000_609075.html.