Design of in-chip oscillator based on CPLD

Clock is an indispensable part of most digital system designs, and external active or passive oscillators are usually used to provide clock signals. The advantage of external clock is stable performance and simple design. The disadvantage is that the area of the printed circuit board will be increased, and the high frequency design requires strict wiring and processing of the printed circuit board, which may increase system cost and design difficulty. The design of a programmable logic device (PLD) based on the field programmable device (field programmable device) or CPLD provides another option, that is, to use in-chip programmable resources for the oscillator function. This design can integrate the oscillation part into the field programmable gate device/CPLD at the same time, reducing the use of external resources.

Ring oscillator is the simplest oscillator design method and has been concerned in the design of discrete devices and special integrated circuits (ASIC) [1,2,3]. However, in such designs, the characteristic of oscillation frequency varying with voltage limits its application, so the stability of oscillation frequency should be considered in process or circuit design. With the development of circuit manufacturing technology, the voltage regulator circuit has been of high quality and low cost. In addition, the manufacturer of the field programmable gate (GA) and CPLD preset some specific modules in the chip, which facilitates the on-chip implementation of the oscillator. For example, Altera's MaxII series CPLD chips allow users to invoke the system-provided parameterized module library (LPM) through the software Quartus II's MegaWizard:Plug-in Manager function. The IO/MAXII Oscil-lator [4] module is a soft core which can implement the on-chip oscillator inside the chip. Its operating frequency range is from 3.33MHz to 5.56MHz, and users cannot adjust the operating frequency. For simulation applications, choose 3.33 or 5.56MHz; In practical applications, the oscillation frequencies in the range of 3.33 to 5.56MHz are automatically given. The on-chip oscillator module can only be downloaded on the user flash memory (UFM) in MaxII series chips. The oscillator output can drive the pins and internal logic of the chip. Once used as an oscillator, the UFM resource can no longer perform other functions such as parallel interface (PIO), serial connection (SPI), and IIC interface.

This paper introduces a general CPLD-based on-chip oscillator design method, which is based on the principle of ring oscillator. It only takes up on-chip common logic resources (LE) and does not need dedicated logic resources (such as UFM in MaxII), thus improving the resource utilization of the chip. The oscillation frequency can be adjusted within a certain range, and the oscillation output can drive pins of internal logic and external devices. This design is more versatile and can be easily ported between different CPLD devices, so that some CPLD-based on-chip system (SoC) designs do not need to use external clock signal source, which reduces the design cost and difficulty, and increases the system integration. Experiments on Altera's MAX7000 series EMP7128LC84-15 chip demonstrate the method. The experimental frequencies range from 8MHz to 62MHz. The simulation and hardware test results show that the design method is correct and feasible.

1 On-chip ring oscillator based on CPLD

The principle of a ring oscillator is shown in Figure 1. A ring cascade composed of odd number of non-gates makes the circuit unstable. Statically, the input and output of any non-gate can not be stable at high or low level, but can only be in a cycle of high and low level transition, thus generating a self-excited oscillation [5]. The oscillation period is T=2N tpd, where N is the number of non-gates and TPD is the transmission delay time of each non-gate. Changing the number of non-gates in the circuit can change the oscillation frequency of the circuit.

The ring oscillator shown in Fig. 1 can not get the corresponding circuit structure even if it is input by schematic diagram and synthesized by EDA software. In fact, the EDA synthesis tool does not start from the structure of the circuit, but from the logical relationship between the input and output of the circuit. Therefore, an odd number of cascades of non-gates will be combined into a non-gate, while an even number of cascades of non-gates will be combined into a buffer or a connection. In order to implement the ring oscillator structure of Figure 1 in CPLD devices, the single-port input element in Figure 1 is changed to a two-port input element, that is, two-input and non-gate are used to replace one of the non-gates in Figure 1, the other even-number of non-gates are replaced by two-input and gate, one input port of the two-port element connects the upper output, and the other input port is used as the control end. The control end of the oscillator is set at a high level when it works normally. The schematic diagram synthesized with Synplify Pro 7.7 is shown in Figure 2. The circuit can fully implement the function of Figure 1.

To ensure positive feedback, the number of non-gate cascades in Fig. 1 structure must be odd. In Figure 2, the non-gate acts as the opposite, while the other gate acts as the delay buffer. The oscillation frequency of the OSC output can be changed by changing the number of gates and selecting the type of gates (and gates, non-gates, etc.) without the limitation of "odd" gates, which can produce oscillation as long as the gates are guaranteed positive feedback. The structure of Fig. 1 must change even number of non-gates in order to change the oscillation frequency. Therefore, the structure of Fig. 2 can save logical resources when implemented in CPLD chips. The control end oscena [n-1,0] is the oscillation enabling control end. At a high level, the input and output of the non-gate produce self-oscillation under the feedback of the buffer cascade chain, and the oscillator works normally. Zero at any position on the control end stops the oscillator. So oscena can be used either individually or as an end when connected. Experiments show that the structure of Figure 2 can guarantee the equal interval characteristic of door delay.

Implementation and optimization of 2 CPLD on-chip oscillator

Implementation of 2.1 CPLD in-chip oscillator

The design of on-chip ring oscillator based on the above method is very versatile and can be easily ported between different CPLD chips. This paper takes the implementation and test of MAX7000S series CPLD chip of Altera Company as an example. The MAX7000S series is based on advanced multi-matrix architecture design and is manufactured using CMOS technology with a capacity of up to 256 logical units LE (Logic El-ement), and consists of a logical array block LAB (LogicArray Block) for every 16 macro units. It has a 3.5ns pin-to-pin delay and supports multiple I/O voltage standards.

From the EDA software synthesis report, it can be seen that each door in the circuit shown in Figure 2 occupies a logical unit. That is to say, the delay of LE in the circuit will be the delay TPD of the gate, and the oscillation will lead to the I/O pin. When the oscillation frequency is low, more gate circuit units are needed, which will occupy certain logic and pin resources and reduce the utilization rate of chip resources. Therefore, when using in low frequency, the oscillation frequency needed by the system should be considered comprehensively, and the ring oscillator should be implemented with fewer gate circuits. To provide a higher oscillation frequency, the crossover circuit is redesigned to obtain an appropriate oscillation frequency, thereby improving the resource utilization of the chip. This treatment of the synthesizer objectively ensures that the designer can choose different gates to implement the structure of Figure 2, and still ensures the consistency of oscillation intervals. Experiments have also confirmed this result.

Effect of 2.2 Power Supply Voltage

Voltage will affect the operating frequency of the oscillating circuit [6]. Increasing voltage will cause the oscillating frequency of the circuit to increase, and vice versa, the oscillating frequency to decrease. CPLD chips generally have two relatively independent power supply ports, namely voltage (VCCINT) and pin voltage (VCCIO). Voltage supplies power to the internal programmable logic circuit resources of the chip, pin voltage supplies power to the I/O pins of the chip to meet various output standards (such as LVCOMOS, LVTTL, SSTL-2, SSTL-3, etc.). The voltage of CPLD chip affects the oscillation frequency. The voltage should be regulated according to different application requirements. The easiest way is to use a high-performance voltage stabilizer chip to provide two parts of the voltage to the CPLD chip. With the development of semiconductor technology, simple and inexpensive voltage stabilizer chips have higher performance, such as National LM2678 series chips [7] within the range of effective input variation, the error of voltage regulator output is within (+) 2%.

2.3 CPLD On-chip Oscillator Optimization

Optimizing the design by EDA software may improve the performance of the designed oscillator and reduce the consumption of CPLD on-chip resources. When using MAX+plusII10.2 software design, the software optimization switch is set to: (1) MAX series chips are selected in this design, so multi-level synthesis for Max5000/7000/9000De-vice is selected. (2) In the area and speed optimization options, choose to optimize the area so that the oscillator part can be allocated to the same LAB as possible. (3) Turn on Slow Slew Rate to reduce switching noise and turn on XOR Synthesis to reduce chip area usage.

3 Circuit simulation and test results

In this paper, MAX+plus II 10.2 of Altera Company is used as design tool to implement and test on MAX7000S series chips. Figure 3 shows the time series simulation results using EMP7128LC84-15 chip. P0-p7 are circuit nodes behind a single gate in a ring oscillator circuit. Oscena [7...0] is the control end of each delay gate circuit (that is, the redundant input end in all two input gates).

Table 1 lists test data for in-chip oscillators with different gate numbers using the Tektronic TDS2012 oscilloscope with EPM7128LC84-15 as the target chip. F1 and F2 represent measurements of in-chip oscillator output and bisector output, respectively. Figure 4 shows the curve of the measured data.

Table 1 shows that the frequency of the oscillating circuit can be reduced regularly by increasing the number of gate circuits, and the delay TPD of the gate circuit unit implemented by each logic unit is between 7.5 and 10ns.

The design method of on-chip oscillator based on CPLD is introduced. When the number of gate circuits in the oscillator circuit is changed, the oscillation frequency can be regularly controlled in the range of 8 MHz to 62 MHz. The in-chip design of the oscillator makes the CPLD-based on-chip system (SoC) design without external clock signal source, which increases the system integration and reduces the design cost. This method is very versatile and can be easily ported between different CPLD chips. The simulation and test data show that the design method is correct and feasible.

Reference:

[1].CPLDdatasheethttp://www.dzsc.com/datasheet/CPLD_1136600.html.
[2].MAX7000datasheethttp://www.dzsc.com/datasheet/MAX7000_1018713.html.
[3].n-1 Datasheethttp://www.dzsc.com/datasheet/n-1_1997158.html.
[4]. MAX7000S Datasheethttp://www.dzsc.com/datasheet/MAX7000S_1018714.html.
[5].LM2678 Datasheethttp://www.dzsc.com/datasheet/LM2678_1060917.html.

Source:Xiang Xueqin