Several Loopback Forms of LXT384 Interface Chip

Abstract: LXT384 is an inbound T1/E1/J1 line interface unit chip for SONET/SDH devices. In this paper, several different forms of loops (analog loops, digital loops, transport loops, etc.) for self-checking of the chip in practical applications are briefly described, and the characteristics and differences of the various forms of loops are intuitively pointed out.

Keywords: LXT384SDHT1E1 Loop

1 Introduction

LXT384 is an octal short-time pulse code modulation (PCM) line interface unit chip produced by Intel Corp. It is commonly used in 1.544 Mbps (T1) and 2.048 Mbps (E1) systems. It is packaged in 144-foot LQFP or 160-bead PBGA, with 8 separate receivers and transmitters.

The sending signal waveform of LXT384 complies with G.703 and T1.102, and the low impedance transmission model provided by its sending driver can accommodate variable driving voltage. It even outperforms send loss provisions such as ETSIETS-300166. All transmitters can switch to high resistance state quickly in power-off mode. The differential input structure of LXT384 enables it to have a high noise interference tolerance, even when the cable is up to 12dB lossy. The optional digital clock recovery PLL and the fluctuation attenuator are related to their 1.544MHz or 2.048MHz clocks.

2 Loopback Mode

LXT384 provides three types of loops (analog, digital, and transit loops), which provide a very good means for self-diagnosis of the system. In hardware mode, the loopback function is enabled by the LOOPn pin (n values 0 to 7); In software mode, ALOOP, DLOOP, and RLOOP registers are used to decide which loopback form to use.

2.1 Analog Loop

Once this loopback is selected at design time, the output (TTIP and TRING pins) of the LXT384 transmitter will be connected to the input (RTIP and RRING pins) of the receiver inside the chip. Its specific structural principle is shown in Figure 1. In this mode, if RTIP and RRING pins are connected with external signals, the external signals will be ignored by LXT384.

2.2 Digital Loopback

The digital loopback form can only be used when LXT384 is configured in software mode. When this form is selected, the send clock and data inputs (TCLK, TPOS and TNEG) and the output of RCLK, RPOS and RNEG pins are looped back (see figure 2). Data on TCLK, TROS and TNEG pins are also output from TTIP and RTING pins. External signals on RTIP and RRING pins are also ignored by LXT384 in this form.

2.3 Remote Loopback

In the LXT384 remote loopback (shown in Figure 3), the outputs of RCLK, RPOS, and RNEG are all fed into the sending circuit and output from TTIP and TRING pins. It should be noted here that the input signals on TCLK, TPOS and TNEG pins are ignored by LXT384 during remote loopback.

2.4 Full "1" Transport (TAOS)

In hardware mode, you can enter TAOS mode by raising the level on the TCLK pin more than 16 MCLK clock cycles. In software mode, enable TAOS mode by writing corresponding bits in the TAOS register. In addition, automatic ATS insertion (assuming LOS status) may be enabled through ATS registers. In this mode, TAOS generator will use MCLK signal as reference clock, so TAOS cannot work in data recovery mode. To ensure that the output frequency is within the specified range, MCLK must be stable. Because digital loopback cannot be enabled when in TAOS state. Figure 4 gives a brief description of the different loops in the TAOS state.

3. Conclusion

In SONET and SDH devices, LXT384 chip is a very important chip. Its main function is to process different data to make the data conform to the rate of T1 and E1 for subsequent processing.

This loopback function of the LXT384 chip enables the LXT384 to judge its own faults without the need for cosmetic signals, which is very useful in chip debugging and fault diagnosis. Understanding the various loopback modes and configuring and using them correctly will make debugging more efficient.

Source:Xiang Xueqin