Raster Ruler Signal Intelligent Interface Module Based on GA

Abstract: A multifunctional raster ruler processor circuit based on the large-scale programmable logic device EPF10K10 of Altera Company is introduced. The design principle of the main circuit of the circuit - quadruple frequency subdivision, direction discrimination circuit, counting circuit and interface processing circuit is described. Detailed circuit and simulation waveform are given in the wind.
Key words: raster ruler quadruple frequency subdivision to identify EDAFPGAEPF10K10

1 Raster Ruler Signal and Circuit Design Requirements

A raster sensor consisting of a light source, two long rasters (moving ruler and fixed ruler), photodetector components, etc. is usually called a raster ruler. The raster ruler outputs electrical signal. When the ruler moves a distance, the output electrical signal changes by a period. It measures the relative displacement between the moving and the fixed position by measuring the period of signal change. The output signal of the raster ruler currently used has two forms, one is square wave signal with phase angle difference of 90o, the other is four sinusoidal signals with phase difference of 90o in sequence. The spatial position period of these signals is W. In this paper, the raster ruler for output square-wave signal is discussed. For output sine-wave signal, the raster ruler can be reshaped to output square-wave signal.

The raster ruler of the output square wave has three electric signals: phase A, phase B and phase Z. Phase A is the main signal and phase B is the secondary signal. The two signal cycles are the same, and the phase difference is 90o. The Z-signal can be used as a more accurate signal to eliminate the cumulative error.

Figure 1 shows the change of A and B signals when the ruler is moved. The direction of motion can be determined by collecting B signals along the descent of A signals. The first half of the figure is in positive motion. The rising and falling edges of A signal are 1/4W ahead of B signal, and the B signal collected along the falling edge of A signal is "1". The second half is in reverse motion. The rising and falling edges of A signal lag 1/4W behind that of B signal, and the B signal collected along the falling edge of A signal is "0". The total displacement can be measured by calculating the curve (forward or reverse) with the counter according to the direction of the collected motion signal and the number of periods of change of the A signal.

In the above signal processing and measurement circuit, triggers, counters and other digital integrated circuits are used, and the measurement resolution is raster distance W. At present, the scale for measurement is usually 50-250 lines per millimeter, and the corresponding spacing W is 20-4 μ M, in precision measurement often can not meet the requirements, and needs to be subdivided by curve. Four subdivisions of signal can be achieved by considering both the rising and falling edges of A and 90o signals. The main circuits are subdividing direction, counting and interface circuits. These functions can be accomplished by universal digital integrated circuits, but this design method uses many chips and is complex in structure. Of course, it can also be completed by the single-chip computer and some peripheral chips, but this method is not universal, complex to program, and increases the burden of the single-chip computer, making the real-time performance of the single-chip computer to respond to other events worse.

With the rapid development of large-scale programmable logic devices (CPLD: complex programmable logic devices; field programmable gate array) the traditional circuit design methods have been greatly improved. Many traditional logic circuits can be completely replaced by programmable logic devices, which can improve the reliability of the system, reduce the area of PCB, make products smaller, and help protect intellectual property rights. Using EDA (Electronic Design Automation) technology to design programmable logic devices has become an inevitable trend in modern electronic design. The interface module of the circuit described in this paper is based on the chip of the field bus.

The circuit design has the following requirements: using the chip of the field bus to complete dual-channel raster ruler signal processing (considering the application of 2-D X-Y platform), four subdivisions and direction distinguishing function, 24-bit reversible counter, parallel interface circuit with microprocessor and various single-chip computers (including latch, decoding, zero clearing circuit, etc.). Its external interface signal is shown in Figure 2.

INA1, INB1, INA2 and INB2 are two A and B signals respectively. As the input signal of the processing circuit, these two signals, after four subdivisions and backward discrimination, can provide counting pulse and direction signal for two 24-letter reversible counters. Interface circuits include latch, decoding, zeroing circuits, etc. Read and write control and external microcontroller interface through data line D0~D7, address line A0~A4, chip selection signal line CS. The interface uses an 8-bit data bus, and data exchanges such as count values (48 bits, 6 reads) and zeroing commands are accomplished by reading and writing to different port addresses. The operation of this module is similar to other smart interface devices such as 8255, 8253, etc.

2Selection of the devices for the field programmable gate device

According to the design requirements and the comprehensive estimation of the number of pins and macro units needed for the entire circuit, EPF10K10 is selected for this design. It is one of the FLEX10K series products of Altera Company and is an embedded programmable logic device. EPF10K10 uses the CMOSSRAM process, and uses the right SRAM to store programming data, which has the programmable feature in the system. There are two specific configurations, passive and active. Passive configurations use special download cables to configure chips, which are generated by the computer through compilation of files suffixed with SOF after power-on. The active configuration is automatically configured by a special programmable configuration chip (such as EPC1441) after power-on. EPF10K10 has features of high density (10,000-250,000 usable logic gates; RAM; 6114-4096 bits, 512 macro units), high speed and low power consumption. The chip contains dedicated carry chain, cascade chain and fast channel, so its interconnection mode is very flexible.

3 Circuit Design

The circuit is designed using Altera's Max-plus development platform. Max-plus is Altera's specialized development platform, which includes functions such as design input, compilation, simulation, device programming, and so on. The platform is easy to use and allows users to design with schematic, VHDL language, waveform and other input methods. The design of the main circuit of the system is described below.

3.1 Subdivision Direction Discrimination Circuit

The subdivision and direction discrimination of raster ruler signal is a key step to improve the measurement of raster ruler. In the data referenced by the author about the raster orientation and subdivision circuit, many designers do not take into account the complexity of the discrimination and subdivision circuit, but separate the discrimination and subdivision circuit. The discrimination circuit only distinguishes the output signal of the raster ruler, not the subdivided pulse signal. Thus, the measurement error is still the raster distance of the raster ruler. When considering the direction discrimination function, the subdivided signal should be designed for direction discrimination, otherwise the measurement cannot be improved.

The schematic diagram of the subdivision direction discriminating circuit is shown in Figure 3. The square wave signals INA and INB with 90 o difference are filtered by RC and reshaped by Schmidt. The output signals A and B are transformed into A', B'signals by level D trigger and A', B' signals by level 2 D trigger. The D trigger can be used to reshape the signal, thus eliminating the impact of sharp pulses in the input signal. As a result, the original signals A and B are no longer used in the subsequent doubling frequency circuit, thus improving the anti-jamming performance of the system. The clock of D trigger is provided by external active crystal oscillation, and its frequency is 1MHz, which is much higher than the frequency of A and B waveform change. Therefore, it can be thought that the output Q of D trigger can track the change of input D. In the quadruple frequency direction discriminating circuit, the logical combination of A', A', B', B'signals is implemented by combination and time sequence logic.

When the raster ruler is moving forward, a quadruple frequency pulse is output from the CLKADD signal end, while there is no signal output from the CLKSUBB end. When the raster ruler is in reverse motion, a quadruple frequency pulse is output from the CLKSUBB signal end, while there is no signal output from the CLKADD end. The CLKADD and CLKSUBB phases, together with the counting pulse CLK which acts as a reversible counter, read out the value of the counter to get the position where the raster moves. An RS trigger circuit consisting of CLKADD and CLKSUBB signals can generate ENADD, ENSUBB. ENADD can be used as the direction signal of the reversible counter. The simulated waveform is shown in Figure 4.

3.2 Counting Circuit

The 24-bit counter in this system is designed in VHDL language. The input signal is defined as clock CLK, direction signal fx=ENADD, and clearing signal CLR (described later). The output signal is defined as a 24-bit count result COUNT (23:0). The 24-bit reversible counter function is written in VHDL language. The simulated signal is shown in Figure 5.

3.3 Interface Circuit

The interface circuit is designed by schematic method. The circuit consists of the following parts:

(1) Address decoding circuit: the input signal is the external (microprocessor, single chip computer, etc.) address line A0~A4, slice selection signal line CS, read and write control signal, through the connection of the logic gate circuit to form the combination logic, to provide enable signal to each internal unit.

(2) Lock-in interface circuit: Because the internal counting units work in a dynamic process, the external microprocessor (or single-chip computer, etc.) should first issue a lock signal to the microprocessor (or single-chip computer) when reading data, and then read the data to ensure stable data reading. The latch output is designed as a three-state gate output, connected to an external data line, and the enabling signal of the three-state gate is provided by the decoding circuit.

(3) Zero-clearing circuit: Zero-clearing circuit is designed in the circuit. The zeroing pulse is decoded internally by an external write command (8 bits), instead of using a signal line to zeroing, which can effectively prevent false zeroing caused by interference when only one signal line is used.

4 Concluding remarks

After the design is simulated and compiled, the code is downloaded to EPC1441 programmable configuration chip, which belongs to the active configuration mode. EPF10K10 chip is automatically configured by EPC1441 when the interface module is powered on. The interface module has been successfully applied to the motion control system designed by the author. The four-subdivision processing function of the raster ruler (position feedback unit in the motion control system) signal has been successfully completed, and the performance is stable and reliable. If this design is combined with decoding driver and display circuit, it can be used independently as displacement measurement and display circuit.

Reference:

[1].EPF10K10datasheethttp://www.dzsc.com/datasheet/EPF10K10_300893.html.
[2]. CPLDdatasheethttp://www.dzsc.com/datasheet/CPLD_1136600.html.
[3]. PCBdatasheethttp://www.dzsc.com/datasheet/PCB_1201640.html.
[4].FLEX10Kdatasheethttp://www.dzsc.com/datasheet/FLEX10K_328755.html.
[5].EPC1441 Datasheethttp://www.dzsc.com/datasheet/EPC1441_300884.html.