Designing paperless recorder with C51 and plug-in FLASH flash memory (Fig.)

In the past, many paperless recorders used 3.5 inch floppy disk as the data storage medium, but many drawbacks such as poor reliability, limited storage capacity and high cost of floppy disk storage are really difficult to overcome.

As a high-tech non-volatile storage device, FLASH flash memory was first applied in digital products such as digital cameras, PDAs, mobile phones and so on. With the progress of technology and the decrease of price, FLASH flash memory is gradually expanding into other application fields. Its advantages such as large capacity, low power consumption, fast speed and not easy to be damaged are becoming more and more popular, and the advantage is that with the progress of technical level, FLASH flash memory capacity is also increasing to 128M, and the interface method has not changed, which avoids the time-consuming and laborious redesign. FLASH flash memory is divided into plug-and-drop type. At present, most domestic manufacturers use patch type to weld FLASH flash memory directly on the printed circuit board. This kind of application makes FLASH flash memory cannot be changed and moved once it is welded properly. Plug-and-drop type can expand and carry conveniently as needed, and is very suitable for applications with uncertain capacity and need to move. For these reasons, we use plug-and-drop FLASH flash memory as the storage device of the paperless recorder.

The design and implementation of a paperless recorder using C51 as the development tool, AT89C55WD single-chip computer and plug-and-drop FLASH flash memory as the memory are briefly described below.

1. General layout of paperless recorder

The function that the paperless recorder achieves is as follows: the recorder has four channels, sampling once per second, recording two bytes per channel, writing the sampled data to the external data memory 62256 according to the dump rate of each channel (which can be set from 1 to 255), and writing 512 bytes to the FLASH flash memory once the data has reached 512 bytes.

Figure 1: Overall function diagram of recorder

The overall function diagram is shown in Figure 1.

2. System Circuit Composition

The circuit of the paperless recorder consists of single-chip AT89C55WD, LCD display circuit, A/D acquisition circuit, FLASH flash memory storage circuit, clock circuit and watchdog circuit. The components are briefly described below.

1. Single-chip AT89C55WD and circuit composition

AT89C55WD is compatible with MCS-51 and can write to the kernel 1000 times with low voltage, current and power consumption. It has a 20K rewritable flash memory and a hardware watchdog timer.

The watchdog timer is a method of recovering from a system software crash. WDT consists of a 14-bit counter and a watchdog reset special function register (WDTRST SFR). By default, the watchdog timer is turned off when the system is reset. To make WDT valid, users must write 01EH and 0E1H to the WDTRST SFR sequence of 0A6H cells. When WDT is valid, the counter is added 1 after every machine cycle. There is no way to invalidate WDT except for hardware or WDT overflow reset. When the counter overflows, WDT produces a reset high pulse on the RST pin.

For WDT to remain valid, 01EH and 0E1H must be written to WDTRST at regular intervals to avoid WDT overflow. When the WDT's 14-bit counter counts to 16383 (3FFFH), the counter overflows, causing a reset of the device. This means that the user must reset the WDT at least every 16383 machine cycles. For WDT reset, 01EH and 0E1H must be written to the write-only register WDTRST. When WDT overflows, a reset high level pulse is generated on the RST pin for a duration of 98 × TOSC, TOSC=1/FOSC. In order to make full use of WDT, WDTRST should be written at regular intervals when WDT overflow reset is required.

Single-chip AT89C55WD drives LCD through P0 port. The sample pulse of AD7715 is output as T1, and the sample data of AD7715 is read in with P2.6 pin at the same time. Because the 8 data lines and address lines of FLASH are multiplexed, the level is converted and connected with FLASH through a 74ALS244 and TC4010BP chip with the port of the single chip computer. The pulse input of the clock DS1305 is 74ALS32 with the P2.4 of the single chip computer. INT0 is connected with the boot 6 of the clock, INT0, so that the DS1305 produces an interrupt signal per second as the beginning of the sampling of AD7715. By using the pulse input to the clock DS1305 as the input to the watchdog X25045, the watchdog function is achieved by writing data to X25045 through P2.6.

2. LCD display circuit

The HG16501 dot matrix LCD monitor is used in the recorder. It has a built-in T6963C control chip and is easy to interface with single-chip computer.

3. A/D collection circuit

The A/D acquisition circuit is mainly composed of AD7715. The chip is a serial input with three-line interface, and HCF4051 is selected as the input of four channels.

This circuit is mainly a level conversion circuit between 5V and 3.3V. This design uses three pieces of TC4010BP.

5. Clock Circuit

The system clock uses the serial clock chip DS1305 and works in the Motorola SPI mode. The INT0 of DS1305 is directly connected to the single-chip computer INT0. DS1305 interrupts every second to start AD7715 for sampling.

6. Watchdog circuit

The system reset-proof watchdog circuit is implemented by programmable X25045, which has three functions: watchdog timer, voltage monitoring and EEPROM. This combination reduces the cost of the system and saves the space of the circuit board.

3. System Software Section

The system software is compiled in C51 language and A51 assembly language, in which the interrupt sampling part is compiled in A51 assembly language.

1. Programming Language

This system uses Keil V6.10's C51 compiler. A51 is a repositioning macro assembler with universal machine usage. It is well compatible with INTEL's MASM51 macro assembly. It supports modular programming and is easy to interface with languages. However, it is quite different from MASM51, mainly because A51 does not support many registers of MASM51.

2. Work process

When the system is powered on and the chips of clock, LCD HG16501 and AD7715 are initialized, the main program is in the cyclic state of detecting keys on the keyboard, and processing them accordingly according to the keys. The collection part is performed by the interrupt generated by the CPU per second. Four channels collect, write 512 bytes to the external memory 62256 before write permission. The main program writes 512 bytes to the FLASH flash memory and resets the write permission as soon as it finds the write permission. Because the software is a hierarchical menu structure, every time you enter the next submenu, you must do the same thing. The clock reads and displays, checks if the write FLASH flash memory allows bits to be set, if set, writes data to the FLASH flash, so it is listed as a regular operation separately.

Flowcharts for the main program and general operations are simple, so they are omitted.

The interrupt collection flowchart is shown in Figure 2.

4. C51 and A51 Procedures

The source program of the C51 part of the whole system software is about 70KB, the A51 source program of the interrupt part is about 7.1KB, the HEX file produced by the compilation and connection of the two parts is nearly 16KB, only four-fifths of the 20KB program memory is used, and the remaining 4K is reserved for adding new functions in the future.

Concluding remarks

In the process of developing paperless recorder, we use C51 and A51 mixed programming to develop software, and use FLASH flash memory as memory. Not only does the software have a lot of functions, but also because the memory is stable, reliable, portable and convenient for further data processing.