Peak Detector (Fig.)

The circuit in Fig. 1 is used to detect the peak value of analog signals. It avoids the drawbacks of previous peak detection circuits, such as limited retention time, sensitivity of detection performance to retained capacitance parameters, high-speed buffer with large input resistance, etc. In addition, the circuit achieves analog to digital conversion without special A/D converter.

In the figure, MAX9001 comparer includes: amplifier, 1.25V voltage reference and comparator, amplifier for signal buffering or filtering (e.g. anti-aliasing filter), resistance R1, R2 to limit the value of input signal to 1.23V, signal detection range of peak detector is determined by reference voltage, comparer U5B compares the attenuated input signal with the previously stored peak voltage, if the input signal is higher than the previously stored peak voltage, Then the comparator outputs a high level, allowing 8-bit synchronous counters composed of U2 and U3 to accumulate at the rate determined by the input clock. As the counter value increases, the output of the analog-to-digital converter (DAC) increases. When the input signal is lower than the peak voltage locked in the counter, the comparator U5B outputs a low level and terminates the count. The A/D conversion is completed by MAX5480 (U4). MAX5480 is a parallel interface and 8-bit R-2R DAC. It is configured as a single power mode in this circuit: OUT1 pin is the base voltage input, REF pin is the DAC output, WR, CS pin of DAC is at low level and it is in a "full pass" state. Any change of data bus can be quickly reflected to the output of DAC.

The allowable clock frequency of this circuit is determined by the sum of counter, DAC and comparator delay times. The total delay time in this circuit is 48ns + 500ns + 370ns = 918ns. Any clock with a frequency below 1MHz is allowed to be selected. The choice of clock frequency mainly depends on the swing rate of the input signal. The inverter U1 ensures that the counter value stops counting when it reaches FFH, the U1 output can be used for the input signal overrun indication, and the microprocessor can also read the counter value FFH directly to detect if the analog input exceeds the full range. The CLR signal from the microprocessor is used to control the peak detector. When the CLR is low level counter is reset, the CLR is high level peak detector is in normal operation.