Design of Intelligent Full Digital Phase Lock Loop

1 Introduction

Digital phase-locked loops have been widely used in digital communication, radio electronics and power system automation. With the development of integrated circuit technology, it is possible not only to make single integrated phase-locked loops with high frequency, but also to integrate the whole system into one chip. In the communication circuit based on GA, the full digital phase-locked loop can be embedded as a function module in the GA to form an in-chip phase-locked loop.

A phase-locked loop is a phase error control system. It compares the phase difference between the input signal and the output signal of the oscillator, and generates an error control signal to adjust the frequency of the oscillator to be in the same frequency as the input signal. The so-called fully digital phase-locked loop (DPLL) is a phase-locked loop composed of a digital phase discriminator (DPD), a digital loop filter (DLF), and a digital control oscillator (DCO). The block diagram of the DPLL is shown in Figure 1.

When the phase discriminator and the digital oscillator are selected in the PLL, the performance of the PLL largely depends on the parameter settings of the digital loop filter.

Parameter Settings for 2 K Counters

The loop filter in 74297 uses a K counter. Its function is to count or filter the phase error sequence and output the corresponding carry or borrow pulse to adjust the phase (or frequency) of the output signal of the I/D digital control oscillator so as to achieve phase control and locking.

The selection of the K value in the K counter needs to be controlled by four control lines, and the modulus value is the N-th power of 2. In the phase-locked loop synchronization state, the phase discriminator has neither lead nor lag pulse output, so the K counter usually has no output. This greatly reduces the Miscontrol of the PLL caused by noise. That is, the K counter acts as a filter to effectively filter out the interference of noise to the loop.

Obviously, it is important to select the K value appropriately in the design. A higher K value is beneficial to suppress noise (because a higher K value makes it impossible for the counter to fully account for a small amount of noise interference, so there will be no carry or borrow pulse output), but this reduces the capture band and increases the time for the loop to enter the locked state. Conversely, a small K value accelerates the lock-in of the loop, but the K counter frequently generates carry or borrow pulses, resulting in phase jitter, which in turn reduces the ability to suppress noise.

To balance the conflict between lock time and phase jitter, it is ideal to reduce the setting of K counter and increase the setting when the digital phase lock loop is out of sync. The premise is to detect the working state of the phase-locked loop.

3 Working state detection circuit

Figure 2 is a phase-locked ring detection circuit, which consists of a trigger and a monostable oscillator. Fin is the reference clock of the input and fout is the clock phase-shifting 900 of the output of the phase-locked loop oscillator. Fout feeds a sample of fin into a monostable oscillator.

In the locked state, as shown in Fig. 3, fout has a stable phase relationship with fin. The sampling of fin by fout should be all 0 or 1, which will not excite oscillator oscillation, thus lock will output low level. In unlocked state, as shown in Figure 4, when fout and fin slip between phases, there will be no long period of 0 or 1 when sampling, and the monostable oscillator oscillates to make lock output high level. The determination of the lock-state retention time of a phase-locked loop can be achieved by setting the oscillator's performance. In the design of field bus, it is very difficult to use off-chip components for single stability, and it is also not conducive to integration and code migration. The implementation of monostable oscillator can also be implemented in the field-bus. Using the counter method, a fully digitized triggerable monostable oscillator triggered in both directions can be designed.

Design of 4 Intelligent Phase Lock Loop

The design of the smart full digital phase lock loop is shown in Figure 5. The phase-locked loop and CPU interface circuit is accomplished by registers. For CPU registers, there are two parts: the working state of the phase-locked loop (read-only), and the parameter value of the K counter (read/write). The CPU can read and write the contents of the registers through an external bus.

The CPU can set the phase-locked loop K counter according to the phase-locked loop state. The initial value of K is set to 23 during the actual test, when the capture band of the PLL is large, the lock state can be reached in a very short time, and the lock becomes low level. When the CPU detects this signal, it automatically increases the K value by 1. If the lock is still low, the CPU will continue to increase the K value. Until the lock loop is unlocked, remember its setting value. Set K to the initial value and set to the value after lock, so that the lock will enter the lock state quickly.

There are three options for choosing a CPU: 1. Implement CPU in the chip of a GA. The development of on-chip systems has made it possible. Share CPU with off-chip system. DPLL is mostly used in communication systems, and most communication systems have embedded CPUs. A single inexpensive single-chip computer (such as 89C51) can not only be used for the control of smart phase-locked loop, but also control the external RAM to achieve the initial loading of the field-bus. It is economical and multi-purpose. It depends on the situation.

5 Conclusion

Intelligent all-digital phase-locked loop can be implemented in a single-chip GA. With the help of the phase-locked loop monitoring circuit, the lock-in time of the lock-in loop can be shortened by CPU, and the jitter characteristics of its output frequency can be improved gradually. Solves the conflict between lock time and phase jitter, and greatly improves the transmission quality of information. This phase-locked loop has been used in the digital communication products developed by our university.

Source:Xiang Xueqin