Design and Implementation of USB-CAN-RS232 Bus Conversion Circuit

1 Introduction

With the emergence of a large number of electronic devices and the actual needs of various control systems, various communication networks have emerged one after another. Because their bus structure, communication protocol and transmission characteristics are different, which brings a lot of trouble to the connection between different devices, there is an urgent need for conversion devices between different buses. At present, the popular field communication networks are RS-232, RS422/485, HART, Profield, Dupline, CAN and LonWorks. This paper describes a USB-CAN-RS232 three-bus converter, which has a simple and novel circuit design, is easy to carry and is very practical.

2 Features of various buses

2.1 CAN (Controller Area Netwrok)

CAN is a controller local area network and belongs to the category of industrial field bus. Compared with the general communication bus, the data communication of CAN bus has outstanding reliability, real-time and flexibility, has a higher communication rate (up to 1 Mb/s), a longer communication distance (up to 10 km), a good anti-electromagnetic interference ability, and uses bus arbitration technology, which makes the communication mode flexible and gets more and more attention. It is widely used in the automotive field. Some automotive manufacturers, such as BENZ, BMW, PORSCHE, ROLLS-ROYCE and JAGUAR, use CAN bus to communicate data between the internal control system and detection and execution agencies.

2.2 USB (Universal Serial Bus)

USB (Universal Serial Bus) is a phenotype bus applied in PC. It was proposed by Intel, Microsoft, NEC and other companies. It is a new type of external serial port. The manufacturer of this specification wants to replace the existing interface of external devices with USB. It also has the functions of connection simplification, software auto-detection and hot plug-and-play. USB has the following features:

1) High data transfer rate. USB high speed: 480Mb/s; USB full speed: 12Mb/s; USB low speed: 1.5Mb/s.
2) Data transmission is reliable. USB transactions include error detection mechanisms that ensure data is sent without errors and can be re-processed in the event of an error.
3) Multiple USB devices are connected at the same time, each USB Bus supports the connection of 127 devices.
4) The USB interface can supply power to the device. When the external power supply requires a voltage of 5V and a current of less than 500mA, the power supply can be obtained directly from the USB bus, thus the USB device does not need a dedicated power cord, which reduces the cost of the device.
5) Support hot pulling. USB implements a true "Plug and Play" function. After the device is connected, it is self-detected by USB and automatically configured by software. It can be used immediately after completion without user intervention.

3 Device characteristics

3.1 SJA1000 CAN Bus Controller

SJA1000 is an alternative to Philips'early PCA82C200 CAN controller. It has stronger functions and features as follows:

Complete compatibility with PCA82C200 and its working mode, namely BASICCAN mode;
A 64 byte FIFO structure with an extended receive buffer;
Support CAN2.0B;
Supports 11-bit and 29-bit IDs;
Bit rates up to 1 Mbit/s;
Clock frequencies up to 24MHz;
Supports interfaces with different microprocessors;
Programmable CAN output driver configuration;
The operating temperature range is wide (-40 degrees to +125 degrees).

The footer arrangement of SJA1000 is shown in Fig. 1. It consists of interface management logic IML, information buffer (including send buffer TXB and receive buffer RXFIFO), bit stream processor BSP, receive filter ASP, bit sequence processing logic BTL, error management logic EML, internal oscillator and reset circuit. IML receives commands from CPU, controls the addressing of CAN registers, and provides interrupt and status information to control. The control of CPU writes data to TXB by IML, and data in TXB is processed by BSP and output by BTL to CAN BUS. BTL always monitors CAN BUS and initiates the receiving process when a valid header "hidden level-control level" conversion is detected. The received information is first processed by the bit stream processor DSP and filtered by ASP. The received information is finally written into RXB or RXFIFO only if the ID of the received information matches the ASP test. RXFIFO can cache up to 64 bytes of data, which can be read by the CPU. EML is responsible for error control of modulators in the transfer layer. It receives error reports from BSP, which prompts DSP and IML to make error statistics.

3.2 USBN9603 USB Interface Circuit

The pins of USBN9603 are arranged as shown in Figure 2. It is a standard USB interface circuit and complies with the USB1.0 and USB1.1 protocols. USBN9603 integrates a 3.3V stable power supply, a serial interface engine SIE, multiple USB endpoint buffer FIFOs, an 8-bit parallel microprocessor interface, and a clock source.

The performance of USBN9603 is as follows: low current, low function, external 24MHz crystal oscillator.
Enhanced DMA mechanism supports fast automatic data transfer;
Bidirectional FIFO memory with 644 integrated;
The external processor interface mode can be controlled by software.
Supports 24MHz crystal oscillator and internal 48MHz clock generation circuit;
The clock frequency can be controlled by software.
There are two optional modes for 8-bit parallel interfaces, including address/data multiplexing and non-address/data multiplexing.
Receive and send side buffers are 64B;

4 Hardware Design

The microprocessor used in the circuit is AT89C51 single-chip computer produced by ATMEL company. The hardware connection is shown in Figure 3. CLKOUT of USBN9603 is connected with XTAL1 of AT89C51. The clock output of USBN9603 provides clock input for AT89C51. AT89C51 accesses USBN9603 through parallel address/data multiplexing, and P2.0 of AT89C51 selects USBN9603 via 74HC14 reverse backend with address 0x00-0x1FF. Using SJA1000 as CAN microcontroller, SJA1000 integrates the physical layer and data link layer functions of CAN protocol, which can complete the frame processing of communication data with the address of 0x000-0x0FF. AT82C50 serves as the interface between the CAN controller and the physical bus to provide the bus differential transmission capability and the CAN controller differential reception capability. Three different working modes (high speed, slope control and standby) can be selected through the AT82C50's pin 3. The pin is grounded in a high-speed mode, and high-speed optocoupler isolation is achieved with 6N137, which prevents the interference of in-line signals. MAX232 is used to convert the RS232 level to the TTL level of the microcontroller interface circuit, and at the same time, some bus port working parameters can be set.

5 Software Design

Under the control of the microcontroller, data exchange is carried out among the buses. The microcontroller initializes the working parameters of each bus, sets the clock, register, baud rate, and chooses the appropriate interrupt mode. For SJA1000, it mainly refers to the settings of control register CR, acceptance code register ACR, acceptance mask register AMR, clock divider CDR, bus timer register BTR0, bus timer BRT1, etc. There are four USB transmission modes: control transmission, block transmission, synchronous transmission and interrupt transmission. The control transmission and block transmission are used in this design. The internal registers and FIFO buffers of USBN9603 control each endpoint separately. When receiving an IN tag packet from the host method, the sending endpoint should send data up automatically. If no data is sent, respond to the NAK (Negative Acknowledegment) handshake package. The main program flow is shown in Figure 4.

When designing software, it is important to correctly select the two buses that need to transfer data, which can be selected with software or hardware.

6 Concluding remarks

This 3-bus converter facilitates data communication between devices on different ports, and the conversion rate of USB-CAN can reach 1 Mb/s. If the requirements of field conditions are high and the requirements of adaptability are strong, measures such as dual CPU and data buffer RAM can be used to improve the circuit. This invisibly increases the complexity of hardware circuit and the logic of software design.