Airborne Miniaturization Control and Protection Based on CPLD

With the rapid development of digital electronic technology, it is imperative to learn from foreign advanced experience and technology to promote the development of electronic equipment industry in China. Complex Programmable Logic Device (CPLD), as a foreign large-scale digital device, has been widely used in industrial control and military fields because of its high reliability and flexible logical design.

Airborne radar has strict requirements on transmitter control and protection system (hereinafter referred to as control and protection system), which not only requires complete real-time logical control and protection functions, but also requires strict environmental temperature and vibration conditions. Based on CPLD technology, the airborne miniaturized control and protection uses Lattice's IspLSI1032-60LG programmable logic device, which has good vibration resistance and working temperature range from -55 C to 125 C. In the design process, the real-time and complex logic control of the radar transmitter is achieved by using digital processing technology, and the I/O anti-jamming performance of the transmitter control guarantee is improved by using digital time filter technology. In addition, due to the good on-line programmability of CPLD, the control and guarantee system based on CPLD has a high popularization value in the application of generalization, serialization and combination for medium and small transmitters.

2 Functional Requirements

The control and guarantee system is an important part of the transmitter system. Its main technical requirements are:

(1) Complete the real-time detection of over-temperature, over-voltage, under-voltage, vacuum drop, tube overcurrent, related power supply, etc.

(2) Preheat the transmitter with delay. After the preheat is completed, the high voltage, trigger and excitation processes are executed in sequence.

(3) Provide the pre-adjusted pulse and the front control pulse for the transmitter modulator. Pre-tuning pulse includes turn-on and turn-off pulses. Pre-tuning pulse needs logical protection. Two pulses cannot be at the same time of high level.

(4) Achieve the detection of timer signal of transmitter, with D and D τ Protection function.

(5) Intelligently shut down the transmitter when the control and guarantee system detects a failure.

3 Hardware Composition

Radar transmitter control and protection mainly consists of CPLD, operational amplifier circuit, comparator circuit, I/O interface circuit, pre-tuning pulse forming circuit, control and display circuit. The hardware component diagram is shown in Figure 1.

In Fig. 1, the high-voltage detection circuit amplifies the sensor detection signal and compares the TTL interface signal that produces over-voltage and under-voltage to the CPLD. The high-voltage signal is analogue. For example, the traveling wave tube (TWT) transmitter has a high voltage including cathode and collector voltage of TWT. Overcurrent, overtemperature and Titanium pump current detection circuits provide CPLD overcurrent, overtemperature, vacuum and other related fault signals respectively. The interface circuit mainly receives the differential transmission switch transmitter instruction and working timer signal provided by the radar signal processor. The display circuit indicates the transmitter fault information and working status information. The JATG interface provides an online programming interface for CPLD. In addition, the circuit also provides a +20V power supply for modulated pulse isolation transformer and a +12V power supply for circuit components.

4 How it works

4.1 System Logic Design

The miniaturized control and protection circuit device based on CPLD is CPLD. The system uses 4MHz crystal oscillating clock reference pulse, and the digital counting by CPLD produces a specific time series relationship. Based on the control information, transmitter working status and fault information, the control and guarantee system performs a comprehensive evaluation. The fault information is processed logically to produce fault results, participate in the control of each node, protect and control the transmitter switching process in real time.

The logical relationship between transmitter control and protection is shown in Figure 2. Instruction information includes on-off high voltage command and on-off modulation command. There are two groups of timing signals used in modulator, one is open pulse, the other is off pulse, and the front excitation signal controls the form of lead pulse.

4.2 Power Up Reset and Delay

Power-on reset is very important, which uses hardware external reset and CPLD logical processing reset. The reset circuit is shown in Figure 3. RESET comes from the external RC reset signal. When the clock is stable, a reset signal is generated inside the CPLD to reset the D trigger in each circuit and synchronously clear the counter. Because each I/O port of the circuit is in a transient state on average during the initial stage of power-on, it does not enter a stable working state. This process is actually waiting for the peripheral I/O level to establish stability.

4.3 Pass D, Pass τ protect

Pass D and Pass τ Protection, that is, over duty cycle and over pulse width protection. When D and τ In case of failure, turn off the excitation and trigger immediately to protect critical devices such as TWT. It is difficult to detect and protect in this system. The variable pulse width and pulse repetition frequency make real-time processing of signal time series more complex. And pass D and pass τ The protection principle is simple. Examples are given here.

Assuming that the duty cycle of over-D protection is 12.5%, over τ Protection pulse width 310 μ S. Figure 4 (a) shows the pulse waveform to be measured, with duty cycle D equal to τ/ T, Fig. τ₁Not equal to τ₂, T₁Not equal to T₂.

The reference clock for detection is 4MHz, the CPLD counts from the rise of the pulse to the flip of the level, stops counting when the level drops to the flip and locks the data DATA1, which is τ Values with a resolution of 1/4 MHz and an error of +0.25 μ S. A digital comparison of locked data occurs when DATA1 is greater than 310/0.25 or 1240 τ Failure. Here 1240 digital comparator is designed using ABLE hardware description language, the program is as follows:

Equations

OUT=(I>=^d1240);

END

A D trigger is triggered along the rising edge of the pulse signal. The periodic pulse waveform is generated as shown in Figure 4 (b). The period T1 is counted when the level in Figure 4 (b) is high, and the period T2 is counted when the level is low. Every time the level is flipped, DATA2 is locked into the next cycle count. Using the waveform with appropriate delay along the rising edge of the pulse waveform in Fig. 4(a), the trigger condition for digital comparator comparison occurs when DATA1 8 times larger than DATA2. When D/ τ After a certain number of consecutive failures occur, the fault is confirmed and the corresponding fault signal is output. Over D/ τ The protection logic diagram is shown in Figure 5. Figure 6 shows the D/ τ Protect the simulation results from real-time simulation.

Anti-jamming processing of 4.4 I/O interface

Due to the characteristics of high voltage and high power, it is very important for low voltage control and protection circuit to have high anti-jamming capability. IspLSI1032-60LG CPLD itself has good anti-jamming capability. Since the working frequency of CPLD is 60MHz, external small interference signals for CPLD will be considered as valid signals to participate in logical judgment unless the I/O interface signals are processed by digital filter. In fact, the control of the transmitter is unfavorable, which will cause failure false alarm. If the fault false alarm information is processed incorrectly and the transmitter is shut down, this test may fail. As a result, similar problems exist in the control and guarantee of small-scale integrated circuits in the past and are difficult to solve.

It is relatively easy to solve the anti-jamming problem by using CPLD technology. Figure 7 shows the principle of digital filter technology in practical application. The period of frequency division counting by 4MHz signal is 0.25. μ S × 256 × A 256_16.4ms clock signal with more than 8 pulses in a row is considered to be a real failure, and the interference signal will not cause the failure signal output.

Processing control signals use the same principle to perform related operations when the control information is confirmed to be valid.

5 Concluding remarks

The above control and protection hardware circuit and software design have better real-time control ability and superiority in the face of complex protection logic. The control and protection system based on CPLD has the characteristics of stable performance, strong anti-jamming ability, small size and compact structure, and has higher application value.

Reference:

[1].CPLDdatasheethttp://www.dzsc.com/datasheet/CPLD_1136600.html.
[2].IspLSI1032-60LGdatasheethttp://www.dzsc.com/datasheet/IspLSI1032-60LG_1620958.html.
[3].TTLdatasheethttp://www.dzsc.com/datasheet/TTL_1174409.html.