Design of arbitrary integer half-integer frequency divider based on CPLD

0 Introduction

In the design of digital system, according to different design needs, we often encounter even frequency division, odd frequency division, semi-integer frequency division, and some require equal duty cycle. In the design of digital system based on CPLD (Complex Programmable Logic Device), it is easy to realize odd frequency division consisting of counters or their cascades in various forms of even frequency division and unequal duty cycle, but the implementation of odd frequency division and half integer frequency division with equal duty cycle is more difficult.
Using VHDL (Very High Speed Integrated Circuit Hardware Description Language) and Quartus II 4.2 development platform, this paper designs a half-integer frequency divider which can realize equal duty cycle integer and approximate equal duty cycle. This design method is simple in principle and only needs few CPLD logic macro units.
1 Design Principle
The system design diagram is shown in Figure 1.

Set appropriate counter cycles according to different frequency dividing coefficients, each count value corresponds to a cycle of the input clock signal fi, make Q0 generate high level only along the rising edge of FI and within the appropriate range of counts, logically or operatively operate Q0 and Q1 to get the desired frequency dividing signal fo. The function of Q1 is to complement half clock cycle at the drop edge in odd frequency division, make it equal duty cycle, and produce rise edge of frequency division signal at the drop edge in half integer frequency division to achieve half integer frequency division.

The following describes how to determine the counter cycle and the respective counting ranges for Q0 and Q1 when they produce high level output. For the convenience of description, the following tags are provided: the crossover coefficient is divide (MAX downto 0), where MAX is the bit of the crossover number corresponding to the binary number, and for half-integer crossover, the bit 0 is the decimal place; Q 0_ Count and q1_ Count produces high level counting ranges for Q 0 and q1, respectively, and records that divide (MAX downto 1) is a, divide (MAX downto 2) is b, and divide (MAX downto 0) -1 is C.

1.1 Even and odd frequency division

Counter cycles range from 0 to C. Even frequency division with equal duty cycles is easy to achieve and is not described here. For odd frequency division, only if q0_ Q0 outputs high level when count is less than a, when q1_ Q1 outputs a period of high level when count = a-1. In other cases, Q0 and Q1 are both low level. Then Q0 and Q1 are logically or, the output fo is the desired cardinal frequency division clock signal.

1.2 Half Integer Frequency Division

Counter cycles are 0 to C. If the integer part is even, only if q0_ Q0 outputs high level when count is less than b, when B is less than q1_ Q1 outputs a high level when count is less than a+b. In other cases, Q0 and Q1 are low. If the integer part is odd, only if q0_ Q0 outputs high level when coun < b, when B < q1_ Count < A + B outputs high level, Q0 and Q1 are low in other cases, then Q0 and Q1 logic or the resulting output F0 are required half-integer crossover clock signals.

2 Simulation results and hardware circuit test

Based on the above principle, simulated waveforms with 7 and 7.5 frequencies developed by Quartus II 4.2 are shown in Figures 2 and 3.

Any integer and half integer frequency division can be achieved with only a slight modification of the program.
A data acquisition system consisting of EPM7064SLC84-10 of Altera Company has passed the test with good performance.
3 Concluding remarks
This frequency division method is simple in principle, has some universality, and uses fewer CPLD logical macro units. For example, in EPM7064, the two frequency dividers simulated above only use 7 logical macro units.

Reference:

[1].CPLDdatasheethttp://www.dzsc.com/datasheet/CPLD_1136600.html.
[2]. EPM7064 Datasheethttp://www.dzsc.com/datasheet/EPM7064_301036.html.