K1S3216B9E-FI70T
| Model | K1S3216B9E-FI70T |
| Description | DRAM |
| PDF file | Total 17 pages (File size: 417K) |
| Chip Manufacturer | SAMSUNG |
K1S3216B9E
WRITE (CS Controlled)
t
VS
t
VP
ADV
V
IH
V
IL
t
CVS
t
AVS
A[20:16]
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
AW
A/DQ[15:0]
V
IH
V
IL
Valid Address
Data Valid
Valid Address
Preliminary
UtRAM
t
VP
t
CVP
t
AVH
t
AVS
Valid Address
t
AVH
t
CW
t
CPH
t
BW
CS
UB/LB
t
ADVWE
t
WP
t
ADVWE
WE
t
AVS
Valid Address
t
AVH
t
AVS
t
AVH
t
DW
t
DH
Don’t Care
1. Don’t care must be in V
IL
or V
IH
.
2. A wri
t
e occurs during the overlap(t
WP
) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for sin-
gle byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or
WE goes high or UB/LB goes high. The t
WP
is measured from the beginning of write to the end of write.
3. t
CW
is measured from the CS going low to the end of write.
4. t
AS
is measured from the address valid to the beginning of write.
5. t
WR
is measured from the end of write to the address change. t
WR
is applied in case a write ends with CS or WE going high.
- 10 -
Revision 0.0
December 2006
