K1S3216B9E-FI70T
| Model | K1S3216B9E-FI70T |
| Description | DRAM |
| PDF file | Total 17 pages (File size: 417K) |
| Chip Manufacturer | SAMSUNG |
K1S3216B9E
TIMING DIAGRAMS
READ (CS controlled)
t
RC
ADV
V
IH
V
IL
Preliminary
UtRAM
t
VP
A[20:16]
V
IH
V
IL
Valid Address
t
AADV
t
VP
Valid Address
t
AVS
t
CVS
t
AVH
t
AVS
t
CPH
t
CVS
t
AVH
CS
V
IH
V
IL
V
IH
t
CO
t
BA
t
HZ
UB/ LB
V
IL
V
IH
t
BHZ
t
ADVOE
t
OE
t
ADVOE
OE
V
IL
t
OLZ
WE
V
IH
V
IL
V
IH
V
IL
Valid Address
t
OHZ
t
OLZ
t
AA
V
OH
V
OL
Valid output
Valid Address
V
OH
V
OL
A/DQ[15:0]
t
AVS
t
AVH
t
AVS
t
AVH
Don’t Care
Undefined
1. Don’t care must be in V
IL
or V
IH
.
2. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
3. At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and from device to device interconnection.
4. t
OE
(max) is met only when OE becomes enabled after t
AA
(max).
5. If invalid address signals shorter than min. t
RC
are continuously repeated for over 2.5us, the device needs a normal read timing(t
RC
) or needs to
sustain standby state for min. t
RC
at least once in every 2.5us.
-5-
Revision 0.0
December 2006
